PLL Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$122,700–$214,300 / yr
Posted
1 day ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $204k
This role $168k
$107k $265k
below market most similar roles pay here above market

This role pays less than 75% of similar roles. Most pay $174,250–$233,137 — the blue band above. At the midpoint, this role pays about $168k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3515 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2718 roles with salary data.

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At a glance

TL;DR · PLL Design Engineer

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The PLL Design Engineer joins the Analog-Mixed/Signal group to develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies. The role involves designing high-quality hard IPs to address the escalating complexity of SOC/PHY designs. Key responsibilities include developing PLL/FLL and frequency synthesis architectures using both digital and analog approaches. The engineer will work on DCO/VCO design, including RO and LC types, while implementing Fractional-N, SSC, and Spur and Jitter cancellation techniques. Required skills include proficiency in band gaps, bias circuits, op-amps, LDOs, and feedback compensation. Candidates must perform behavioral simulations and develop System Verilog models to explore architectural performance and loop dynamics. The position requires mastery of phase noise, jitter analysis, and budgeting within a collaborative hardware design environment.

Skills

PLL FLL Frequency Synthesis System Verilog RTL VCO DCO Jitter Analysis Op-Amps Scripting SOC SerDes

What you'll do

  • Develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies.
  • Design PLL/FLL architectures using both digital and analog approaches.
  • Design and implement DCO/VCO circuits using RO and LC techniques.
  • Apply fractional-N, SSC, and spur/jitter cancellation techniques to circuit designs.
  • Develop System Verilog models and perform behavioral simulations to explore architectural performance.
  • Analyze phase noise, jitter budgets, and feedback loop dynamics.
  • Design and debug RTL for clocking and frequency synthesis components.
  • Design supporting analog circuits including band gaps, bias circuits, op-amps, and LDOs.

What we're looking for

  • Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design (preferred).
  • Good understanding of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques (preferred).
  • Deep understanding of clocking fundamentals, including phase noise, jitter analysis, budgeting, and feedback loop dynamics (preferred).
  • Skilled in developing System Verilog models and performing behavioral simulations (preferred).
  • Ability to design/debug RTL (preferred).
  • Outstanding teamwork capabilities paired with strong productivity and scripting skills (preferred).
  • Experience in using industry-standard design tools (preferred).

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