Implementation Timing / STA Design Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
43 days ago
Freshness
Confirmed live yesterday
Closes
Jan 26, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $194k
This role $175k
$130k most similar roles pay here $236k

This role pays less than 68% of similar roles. Most pay $168,200–$219,043 — the shaded band above. At the midpoint, this role pays about $175k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Implementation Timing / STA Design Engineer

Role Posting Log in to save

The Implementation Timing / STA Design Engineer joins the SoC Implementation Team to focus on timing constraints development, power analysis, static timing analysis, and timing closure for premium-tier chips in sub-3nm nodes across mobile, AI, and automotive sectors. The engineer will develop constraints for physical power-aware synthesis, manage multi-voltage domain crossings, and ensure correlation between HM and SoC timing. Day-to-day responsibilities include collaborating with RTL design and physical design teams to identify bottlenecks, validating clock domain crossing constraints, and analyzing path pessimism across various modes and corners. Required technical skills include proficiency with Primetime and Fishtail/TCM tools, along with desirable scripting capabilities in Tcl, Perl, or Python. This role addresses the critical challenge of achieving timing closure for complex SoC cores within advanced semiconductor manufacturing processes.

Skills

STA Primetime Fishtail TCM Tcl Perl Python ASIC Design Timing Closure Power Analysis RTL Design Physical Design Multi-voltage Domain Crossing Clock Domain Crossing Synthesis

What you'll do

  • Develop constraints for physical power-aware synthesis across various modes and corners.
  • Manage low-power multi-voltage domain crossings and signoff with static timing analysis.
  • Generate, review, and validate clock domain crossing and design constraints for complex SoC cores.
  • Integrate HM constraints into the SoC while ensuring correlation between HM and SoC timing.
  • Analyze timing across various modes and corners to address path pessimism and margins.
  • Identify timing requirements and bottlenecks in coordination with RTL and physical design teams.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field with 4+ years of ASIC design, verification, validation, or integration experience.
  • Master's degree in Science, Engineering, or a related field with 3+ years of ASIC design, verification, validation, or integration experience.
  • PhD in Science, Engineering, or a related field with 2+ years of ASIC design, verification, validation, or integration experience.
  • Proficiency with tools such as Primetime and Fishtail/TCM.
  • Experience in timing constraints development, power analysis, STA, and timing closure for premium-tier chips.
  • Ability to develop constraints for physical power-aware synthesis and low-power multi-voltage domain crossings.
  • Capability to analyze timing across modes and corners while understanding path pessimism and margins.
  • Desirable scripting skills in Tcl, Perl, or Python.

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