Implementation Timing / STA Design Engineer

Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $140,000–$210,000 / yr
Posted: 10 days ago
Closes: Dec 15, 2026
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $181k

This role $175k

$131k most similar roles pay here $222k

This role pays more than 51% of similar roles. Most pay $151,826–$209,750 — the shaded band above. At the midpoint, this role pays about $175k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 834 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 514 roles with salary data.

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At a glance

TL;DR · Implementation Timing / STA Design Engineer

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Qualcomm’s SoC Implementation Team seeks a mid-level engineer to develop timing constraints, perform power analysis, and ensure static timing closure for premium-tier chips in sub-3nm nodes across mobile, AI, and automotive sectors. The role involves creating physical power-aware synthesis constraints, setting up modes/corners, and validating low-power multi-voltage domain crossings while collaborating with RTL design and physical teams to identify timing requirements and bottlenecks. Essential skills include proficiency with Primetime, Fishtail/TCM, and scripting in Tcl, Perl, or Python. The ideal candidate will have at least 2 years of experience and a strong understanding of concepts like path pessimism and margins.

Skills

Primetime Fishtail/TCM Tcl Perl Python

What you'll do

Develop physical power-aware synthesis constraints for various modes/corners.
Identify timing requirements and bottlenecks in collaboration with design teams.
Generate and validate clock domain crossing and design constraints for timing closure.
Review and integrate hierarchical module (HM) constraints into system-on-chip (SoC).
Analyze timing across different modes and corners to understand path pessimism.

What we're looking for

At least 2 years of experience in SoC implementation.
Proficiency with Primetime, Fishtail/TCM tools for timing analysis.
Strong scripting skills in Tcl, Perl, or Python.
Experience developing constraints for power-aware synthesis and low-power multi-voltage domains.
Ability to collaborate with RTL design and physical design teams on timing requirements.
Expertise in analyzing timing across modes and corners, understanding path pessimism and margins.

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