Implementation Timing / STA Design Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $145,600–$218,400 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k

This role $182k

$131k $277k

below market most similar roles pay here above market

This role pays less than 59% of similar roles. Most pay $169,250–$240,550 — the blue band above. At the midpoint, this role pays about $182k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Implementation Timing / STA Design Engineer

Role Posting Log in to save

JOB TITLE: Implementation Timing / STA Design Engineer The Implementation Timing / STA Design Engineer joins the SoC Implementation Team to support the Snapdragon team. This role focuses on timing constraints development, power analysis, static timing analysis, and timing closure for premium-tier chips in sub-3nm nodes across mobile, AI, and automotive sectors. The engineer will develop constraints for physical power-aware synthesis, handle low-power multi-voltage domain crossings, and validate clock domain crossing constraints to achieve timing closure for complex SoC cores. Key responsibilities include collaborating with RTL and physical design teams to identify bottlenecks and analyzing timing across various modes and corners. Required technical skills include proficiency with Primetime and Fishtail/TCM tools, along with scripting capabilities in Tcl, Perl, or Python to solve complex timing and power requirements.

Skills

Static Timing Analysis Primetime Fishtail TCM Tcl Perl Python ASIC Design RTL Design Physical Design Power Analysis Clock Domain Crossing Timing Closure Synthesis

What you'll do

Develop constraints for physical power-aware synthesis and low-power multi-voltage domain crossings.
Perform signoff using static timing analysis (STA) for premium-tier chips.
Generate, review, and validate clock domain crossing and design constraints.
Achieve timing closure for complex SoC cores.
Review and integrate HM constraints into the SoC while ensuring timing correlation.
Analyze timing across various modes and corners to manage path pessimism and margins.

What we're looking for

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Proficiency with tools such as Primetime and Fishtail/TCM.
Scripting skills in Tcl, Perl, or Python (preferred).
Experience developing constraints for physical power-aware synthesis and low-power multi-voltage domain crossings.
Experience with static timing analysis (STA) and achieving timing closure for complex SoC cores.
Ability to analyze timing across modes and corners, including path pessimism and margins.

Similar roles

Physical Design/Implementation Engineer, Staff

Qualcomm

Austin, TX 40 days ago $145,600–$218,400

ASIC Design Physical Design Synthesis PnR Static Timing Analysis STA Clock Tree Synthesis CTS Floorplanning Routing UPF low-power design Python Tcl Fusion Compiler Genus Innovus ICC2 PrimeTime Tempus LEC Version Control Configuration Management Regression

4+ yrs exp

Save