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Active Keyword: ASIC Design Engineer Remove filter Location: Irvine Remove filter Clear all

14 of up to 20 (filtered)

ASIC Design Verification Engineer

Broadcom

Irvine, CA +2 12 days ago
Actively hiring Confirmed live today High trust
System Verilog UVM Constrained Random Verification VCS Incisive Python Perl SVA OOP Coverage Closure Ethernet AI/ML Scripting
10+ yrs exp
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ASIC Design Engineer

Broadcom

Irvine, CA +2 14 days ago $121,900–$195,000
Actively hiring Confirmed live today High trust Below market
ASIC Design RTL Design Ethernet PCIe Python Perl Simulation Verification Synthesis Timing Closure Silicon Validation Architecture Definition high speed communication front end design
8+ yrs exp
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Senior ASIC Design Engineer

SpaceX

Palo Alto, CA +3 18 days ago $175,000–$280,000
Actively hiring Confirmed live today Trusted Above market
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp
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ASIC Design Engineer

SpaceX

Palo Alto, CA +2 18 days ago $135,000–$175,000
Actively hiring Confirmed live today Trusted Below market
ASIC Design FPGA Verilog SystemVerilog VHDL RTL Design Python C/C++ Bash SoC Integration DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer
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Senior ASIC Design Engineer

SpaceX

Irvine, CA +3 27 days ago $165,000–$265,000
Actively hiring Confirmed live today Trusted Competitive pay
Verilog System Verilog RTL Design ASIC SoC Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp
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FPGA/ASIC Design Engineer

SpaceX

Irvine, CA +1 27 days ago $125,000–$160,000
Actively hiring Confirmed live today Trusted Below market
ASIC Design FPGA Design SystemVerilog Verilog VHDL RTL Design Python C/C++ Bash DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer SoC Integration
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Senior ASIC Design Engineer

SpaceX

Redmond, WA +3 27 days ago $165,000–$270,000
Actively hiring Confirmed live today Trusted Above market
RTL Design Verilog System Verilog ASIC SoC Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems
5+ yrs exp
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Senior ASIC Design Engineer

SpaceX

Austin, TX +3 27 days ago
Actively hiring Confirmed live today Low trust
Verilog System Verilog RTL Design ASIC SoC Synthesis Timing Closure AXI AHB Python HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems Formality Check Silicon Bring-up
5+ yrs exp
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FPGA/ASIC Design Engineer

SpaceX

Redmond, WA +1 27 days ago $125,000–$165,000
Actively hiring Confirmed live today Trusted Below market
ASIC Design FPGA Design SystemVerilog Verilog VHDL RTL Design Python C/C++ Bash DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer
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Senior ASIC Design Verification Engineer

SpaceX

Irvine, CA 105 days ago $165,000–$260,000
Actively hiring Confirmed live today Low trust Competitive pay
ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage Test Plans Scripting
5+ yrs exp
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ASIC Design Verification Engineer

Broadcom

Irvine, CA +2 132 days ago $129,400–$207,000
Actively hiring Confirmed live today High trust Below market
System Verilog UVM Constrained Random Verification VCS Incisive Python Perl OOP SVA Coverage Closure Ethernet AI/ML Scripting
10+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA +2 154 days ago $165,000–$260,000
Actively hiring Confirmed live today Low trust Competitive pay
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Palo Alto, CA +3 154 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Austin, TX +2 154 days ago
Actively hiring Confirmed live today Low trust
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route Physical Verification Electromigration Voltage Drop Logic Equivalency FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools
5+ yrs exp
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