Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Austin, TXIrvine, CAPalo Alto, CARedmond, WA
Posted: 3 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $199k

$140k most similar roles pay here $256k

This listing doesn't post a salary. Most similar roles pay $171,125–$227,500.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 654 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 468 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Senior ASIC Design Engineer, Silicon Engineering

Role Posting Log in to save

Sr. ASIC Design Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for deployment in space and ground infrastructures. This role involves evaluating architectural trade-offs based on performance requirements, defining micro-architecture, and implementing RTL using Verilog and System Verilog. The engineer will integrate designs into the top level, provide timing constraints, support physical implementation through synthesis and timing closure, and participate in silicon bring-up and validation. Key technical skills include experience with embedded CPU subsystems, standard bus protocols like AXI and AHB, high speed and low power design techniques, and scripting in Python. The role addresses the challenge of providing reliable connectivity via the Starlink network by building hardware that enhances performance for global infrastructure. Candidates must possess a degree in electrical, computer, or computer science engineering and have over five years of RTL implementation experience.

What does a ASIC Design Engineer earn in California?

Median $214000 from 45 postings across 7 companies.

See salary data

Skills

Verilog System Verilog ASIC SoC RTL Design Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization

What you'll do

Evaluate architectural trade-offs based on features, performance requirements, and system limitations.
Define micro-architecture for next-generation ASICs used in space and ground infrastructure.
Implement RTL designs using Verilog or SystemVerilog.
Integrate designs into the top level to deliver synthesis and timing clean results.
Collaborate with verification teams to ensure all design aspects are fully covered and verified.
Provide timing constraints and support physical implementation tasks like synthesis and timing closure.
Participate in silicon bring-up and validation processes.

What we're looking for

Bachelor's degree in electrical engineering, computer engineering, or computer science.
5+ years of experience in RTL implementation.
Ability to work extended hours or weekends as needed for mission critical deadlines.
Must be a U.S. citizen, national, lawful permanent resident, or eligible for required export control authorizations.
Ability to solve complex problems including clock domain crossings and power optimization (preferred).
ASIC/SoC system integration experience (preferred).
Experience with embedded CPU subsystems and standard bus protocols like AXI or AHB (preferred).
Experience with high speed/low power design, scripting, and EDA tools (preferred).

Similar roles

Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Irvine, CA +3 3 days ago $165,000–$265,000

RTL Verilog System Verilog ASIC SoC AXI AHB Python EDA Tools HDL Simulators Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up

Save

Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Redmond, WA +3 3 days ago $165,000–$270,000

Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up

Save

Senior SOC/ASIC Physical Design Engineer

SpaceX

Austin, TX 130 days ago

ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route DFT Scan MBIST LBIST FinFET CMOS Python TCL Perl Bash Makefile EDA Tools

5+ yrs exp

Save

Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA 130 days ago $165,000–$260,000

ASIC SOC Physical Design RTL2GDSII Static Timing Analysis (STA) EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis

5+ yrs exp

Save

Senior SOC/ASIC Physical Design Engineer

SpaceX

Sunnyvale, CA 130 days ago $175,000–$280,000

ASIC Physical Design RTL2GDSII STA EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis Electromigration

5+ yrs exp

Save

Senior ASIC Design Verification Engineer

SpaceX

Austin, TX 81 days ago

ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design

5+ yrs exp

Save