FPGA/ASIC Design Engineer

SpaceX

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Redmond, WAIrvine, CA
Salary
$125,000–$165,000 / yr
Posted
2 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k
This role $145k
$112k most similar roles pay here $243k

This role pays less than 88% of similar roles. Most pay $162,000–$223,000 — the shaded band above. At the midpoint, this role pays about $145k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 654 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 468 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · FPGA/ASIC Design Engineer

Role Posting Log in to save

The FPGA/ASIC Design Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation FPGAs and ASICs for space and ground infrastructure. This role involves designing complex SoC blocks, performing integration tasks, and optimizing designs for power, performance, and area throughout the full design lifecycle. The engineer will participate in architectural discussions, microarchitecture development, and lab bring-up while building physical and digital tools to analyze orbital data. Key responsibilities include developing test systems for validation and collaborating with software engineers on production code. Required technical skills include RTL design using Verilog, SystemVerilog, or VHDL, alongside proficiency in Python, C/C++, and Bash. The role also involves experience with AXI/AHB/APB protocols, EDA tools like Vivado or Quartus, and debugging complex PCBs with oscilloscopes to support the Starlink network's communication systems.

Skills

ASIC FPGA Verilog SystemVerilog VHDL RTL Design Python C C++ Bash DSP AXI AHB APB Vivado Quartus II VCS Questa Spyglass

What you'll do

  • Design ASICs and FPGAs for Starlink projects using Verilog and SystemVerilog.
  • Implement complex SoC blocks and manage integration tasks for space and ground infrastructure.
  • Optimize hardware designs for power, performance, and area constraints.
  • Manage the full design lifecycle from high-level architectural discussions to microarchitecture and design partitioning.
  • Build physical and digital tools to analyze data collected in the lab and on orbit.
  • Design test systems to support FPGA/ASIC validation and integration with DSP communication subsystems.
  • Collaborate with software engineers to develop production software for hardware designs.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics.
  • 1+ years of experience in RTL Design using SystemVerilog, Verilog, or VHDL.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, or asylee (or eligible for such status) to meet ITAR requirements.
  • Master's degree in Electrical/Computer Engineering or related field (preferred).
  • Experience with ASIC/FPGA system integration (preferred).
  • Proficiency in Python, C/C++, and Bash (preferred).
  • Experience designing DSP, digital communication system datapath blocks, and/or modem design (preferred).
  • Experience with EDA tools, AXI/AHB/APB protocols, and lab debugging of complex PCBs (preferred).

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