FPGA/ASIC Design Engineer

SpaceX

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Irvine, CARedmond, WA
Salary
$125,000–$160,000 / yr
Posted
11 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $190k
This role $142k
$112k $243k
below market most similar roles pay here above market

This role pays less than 90% of similar roles. Most pay $162,000–$217,500 — the blue band above. At the midpoint, this role pays about $142k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 796 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 555 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · FPGA/ASIC Design Engineer

Role Posting Log in to save

The FPGA/ASIC Design Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation FPGAs and ASICs for space and ground infrastructures. This role focuses on the Starlink satellite constellation, where the engineer will design complex SoC blocks and integration tasks to expand network performance. Key responsibilities include participating in the full design lifecycle, from high-level architectural discussions and microarchitecture to design partitioning and lab bring-up. The engineer will optimize designs for power, performance, and area while building tools to analyze orbital data. Required technical skills include RTL design using Verilog, SystemVerilog, or VHDL. Preferred competencies include proficiency in Python, C/C++, and Bash, experience with EDA tools like VCS or Vivado, knowledge of AXI/AHB/APB protocols, and experience designing DSP or digital communication system datapath blocks.

Skills

ASIC Design FPGA Design SystemVerilog Verilog VHDL RTL Design Python C/C++ Bash DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer SoC Integration

What you'll do

  • Design ASICs and FPGAs for Starlink projects using Verilog and SystemVerilog.
  • Implement complex SoC blocks and perform SoC integration tasks.
  • Optimize hardware designs for power, performance, and area.
  • Manage the full design lifecycle from high-level architecture to microarchitecture and design partitioning.
  • Build physical and digital tools to analyze data collected in the lab and on orbit.
  • Design test systems to support FPGA/ASIC validation and integration with DSP subsystems.
  • Develop production software for hardware designs in collaboration with software engineers.
  • Assist in lab bring-up and validation of new hardware components.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics.
  • 1+ years of experience in RTL Design using SystemVerilog, Verilog, or VHDL.
  • Ability to work extended hours or weekends as needed for mission-critical deadlines.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • ASIC/FPGA system integration experience (preferred).
  • Proficiency in Python, C/C++, and Bash (preferred).
  • Experience designing DSP, digital communication system datapath blocks, and/or modem design (preferred).
  • Experience with EDA tools, AXI/AHB/APB protocols, and lab debugging of complex PCBs (preferred).

Related searches

More FPGA jobs FPGA jobs in Irvine All jobs at SpaceX

More like this

Similar roles

FPGA/ASIC Design Engineer

SpaceX

Redmond, WA +1 11 days ago $125,000–$165,000
ASIC Design FPGA Design SystemVerilog Verilog VHDL RTL Design Python C/C++ Bash DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer
Save

ASIC Design Engineer

SpaceX

Palo Alto, CA +2 2 days ago $135,000–$175,000
ASIC Design FPGA Verilog SystemVerilog VHDL RTL Design Python C/C++ Bash SoC Integration DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer
Save

ASIC/SOC DFT Engineer

SpaceX

Palo Alto, CA +1 66 days ago $135,000–$175,000
ASIC SOC DFT ATPG Verilog SystemVerilog Python Perl Bash csh UPF DRC RTL Gate Level Simulation SDF Formal Verification Synthesis Physical Design
1+ yrs exp
Save

ASIC/SOC DFT Engineer

SpaceX

Austin, TX +1 66 days ago
ASIC DFT ATPG Verilog SystemVerilog Python Perl Bash UPF RTL Gate Level Simulation SDF DRC Formal Verification Synthesis Scan Insertion
1+ yrs exp
Save

Advanced ASIC FPGA Design Engineer

General Dynamics

Scottsdale, AZ 22 days ago $135,396–$150,205
VHDL Verilog SystemVerilog FPGA Xilinx Microchip Vivado Libero QuestaSim ModelSim CI/CD Python Tcl Bash GitLab AXI4 AXI-Stream PCIe Ethernet AES SHA MicroBlaze Zynq Versal AI Engine
5+ yrs exp
Save

ASIC FPGA Engineer

General Dynamics

Pittsfield, MA 53 days ago $94,056–$104,343
ASIC FPGA Synthesis Place and Route Power Utilization System Simulation Device Libraries Microsoft Office AI
1+ yrs exp
Save