ASIC Design Engineer

SpaceX

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Palo Alto, CAIrvine, CARedmond, WA
Salary
$135,000–$175,000 / yr
Posted
2 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $195k
This role $155k
$122k $252k
below market most similar roles pay here above market

This role pays less than 82% of similar roles. Most pay $162,000–$227,350 — the blue band above. At the midpoint, this role pays about $155k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 796 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 555 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · ASIC Design Engineer

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ASIC Design Engineer (Silicon Engineering) The ASIC Design Engineer (Silicon Engineering) works within a cross-disciplinary team to develop next-generation FPGAs and ASICs for space and ground infrastructures. The role involves implementing complex SoC blocks and integration tasks, optimizing designs for power, performance, and area, and participating in the full design lifecycle from architectural discussions to lab bring-up. Key responsibilities include building physical and digital tools to analyze orbital data and collaborating with software engineers on production software. Candidates must utilize Verilog, SystemVerilog, VHDL, Python, C/C++, and Bash. Proficiency with EDA tools like VCS, Questa, and Vivado, along with knowledge of AXI/AHB/APB protocols and DSP datapath blocks, is required. This work directly enables global connectivity by expanding the performance and capabilities of the Starlink satellite network.

What does a ASIC Design Engineer earn in California?

Median $214000 from 51 postings across 8 companies.

See salary data

Skills

ASIC Design FPGA Verilog SystemVerilog VHDL RTL Design Python C/C++ Bash SoC Integration DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer

What you'll do

  • Design ASICs and FPGAs for Starlink projects using Verilog and System Verilog.
  • Implement complex SoC blocks and manage SoC integration tasks.
  • Optimize hardware designs for power, performance, and area.
  • Manage the full ASIC/FPGA design lifecycle from high-level architecture to lab bring-up.
  • Build physical and digital tools to analyze data collected in the lab and on orbit.
  • Design test systems for FPGA/ASIC validation and integration with DSP/communications subsystems.
  • Develop production software for hardware designs in collaboration with software engineers.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics.
  • 1+ years of experience in RTL Design using SystemVerilog, Verilog, or VHDL.
  • Ability to work extended hours or weekends as needed for mission-critical deadlines.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Master’s in Electrical/Computer Engineering or related field (preferred).
  • ASIC/FPGA system integration experience (preferred).
  • Proficiency in Python, C/C++, and Bash (preferred).
  • Experience with EDA tools, DSP/modem design, and AXI/AHB/APB protocols (preferred).

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