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Static/Dynamic IR EM Noise Signal EM ASIC AMS VLSI Redhawk PrimeRail Voltus PrimeTime Tempus SPICE Scripting Computer Architecture Circuit Design Low Power Techniques Tape-out +13 more Show less

SoC Physical Design Electrical Analysis Static/Dynamic IR EM ESD Gridcheck ASIC VLSI Redhawk PrimeRail Voltus Innovus Design Compiler PrimeTime Tempus SPICE Low-power Design Power Integrity Tape-out Digital Systems +15 more Show less

PnR RTL2GDS STA Physical Verification EMIR Sign-off Floorplanning Clock & Power Distribution Timing Closure Deep Submicron Technology SOC Design Power Optimization +7 more Show less

STA Timing Closure Physical Design ECO Perl TCL SPICE SoC OCV Crosstalk Circuit Modeling Netlist to Tapeout +7 more Show less

Static/Dynamic IR EM Noise Signal EM Python ASIC AMS VLSI SPICE Circuit Design Computer Architecture Low Power Architecture Tape-out Sign-off Closure +9 more Show less

STA Timing Closure Physical Design Perl TCL ECO SPICE SoC Netlist to Tapeout Circuit Modeling OCV Crosstalk +7 more Show less

STA Timing Closure Physical Design Perl TCL ECO SPICE SoC Circuit Modeling OCV Crosstalk Netlist to Tapeout +7 more Show less

Physical Design Flow SoC Floor Planning Clock Tree Synthesis Place and Route PDN Timing Analysis LVS DRC Tapeout Micro-architecture Algorithm Design Modeling +8 more Show less

PnR Physical Design VLSI Verilog VHDL Python Perl TCL SPICE STA DRC LVS EMIR Redhawk Totem Voltus GDS2 Floor-planning Physical Synthesis +14 more Show less

LVS DRC ANT HVDRC ASIC Physical Design Physical Verification Mentor Calibre Synopsys ICV Python Perl Tcl Tapeout Layout Design Design-for-Manufacturing Design-for-Yield Lithography RDL ESD Mixed Signal Back-end Verification +14 more Show less

PnR RTL2GDS STA Physical Verification EMIR Sign-off Floorplanning Clock & Power Distribution Timing Closure Deep Submicron Technology SOC Design Power Optimization +7 more Show less

Physical Design TCL Python Netlist to GDS PNR Voltage Drop Analysis STA Layout Verification CAD Electrical Analysis DRC Automation Tapeout +8 more Show less

Physical Design TCL Python ASIC Integration Floorplanning Power Distribution Signal Planning I/O Planning Hard IP Integration PNR Voltage Drop Analysis STA Layout Verification DRC Automation Netlist to Tapeout +11 more Show less

LVS DRC ANT HVDRC ASIC Physical Design Physical Verification Mentor Calibre Synopsys ICV Python Perl Tcl Tapeout Layout Design Design-for-Manufacturing Design-for-Yield Lithography RDL ESD Mixed Signal Back-end Verification +14 more Show less

ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop +17 more Show less

ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop +17 more Show less

ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route Physical Verification Electromigration Voltage Drop Logic Equivalency FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools +19 more Show less