SoC Physical Design Engineer, STA/Timing

Apple Inc

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Work type
On-site
Location
Austin, TX
Posted
40 days ago
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Confirmed live today
Nearby
99+ roles within 25 mi

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

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TL;DR · SoC Physical Design Engineer, STA/Timing

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The SoC Physical Design Engineer, STA/Timing will join the hardware team to manage the physical implementation of design partitions from netlist to tapeout for highly complex SoCs using state of the art process technology. The role involves working with design teams to debug constraints, facilitate logic changes to improve timing, and create timing ECOs for project tapeouts. Key responsibilities include performing deep analysis of timing paths, implementing timing infrastructure, and creating scripts and methodologies for analysis runs. Candidates must possess programming skills in Perl and TCL along with experience in large design STA and timing closure. The work requires a fundamental understanding of noise, crosstalk, OCV effects, circuit modeling using SPICE models, and worst-case corner selection within sub-micron technologies to solve complex timing issues.

Skills

STA Timing Closure Physical Design Perl TCL ECO SPICE SoC Netlist to Tapeout Circuit Modeling OCV Crosstalk

What you'll do

  • Execute physical implementation of design partitions from netlist to tapeout for complex SoCs.
  • Perform deep analysis of timing paths to identify and resolve critical issues.
  • Create and implement timing ECOs for project tapeouts.
  • Develop and maintain scripts and methodologies for analysis and design runs.
  • Implement timing infrastructure for high-performance SoC designs.
  • Debug design constraints and facilitate logic changes to improve timing.
  • Create technical documentation, guidelines, and specifications for the design process.

What we're looking for

  • Minimum BS degree and 10+ years of relevant industry experience.
  • Experience with large design STA and/or Timing Closure.
  • Programming skills with Perl and TCL.
  • Hands-on experience in STA (preferred).
  • Familiarity with timing of large high-performance SoC designs in sub-micron technologies (preferred).
  • Proficiency in STA and methodologies for timing closure with understanding of noise, crosstalk, and OCV effects (preferred).
  • Familiarity with circuit modeling, including SPICE models, and worst-case corner selection (preferred).
  • Familiarity with ECO techniques and implementation (preferred).

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