SoC Physical Design Engineer, PnR

As an SoC Physical Design Engineer, PnR, you will serve as a technical leader focused on high-performance and low-power design within the hardware team. You will manage all aspects of physical design implementation from RTL2GDS, including floorplanning, bump/RDL, STA, physical verification, EMIR, and sign-off. Your daily work involves collaborating with cross-functional teams to develop efficient chip and IP physical architectures while addressing complex timing closure issues, area optimization, and power reduction. You will also establish methodologies, best-known methods, and guidelines to streamline workflows. The role requires expertise in deep submicron technology for large SoC designs exceeding 20M gates at frequencies over 1GHz. You must be proficient with industry standard tools and their underlying algorithms to solve critical physical design constraints early in the cycle while meeting stringent schedule and die size requirements.