SoC Physical Design Engineer, STA/Timing

Apple Inc

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Work type: On-site
Location: Austin, TX
Posted: 16 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $210k

$146k most similar roles pay here $277k

This listing doesn't post a salary. Most similar roles pay $177,250–$241,750.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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TL;DR · SoC Physical Design Engineer, STA/Timing

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As an SoC Physical Design Engineer, STA/Timing, you will be responsible for the physical implementation of design partitions from netlist to tapeout for highly complex SoCs using state of the art process technology. You will collaborate with design teams to debug constraints and facilitate logic changes to improve timing while working with the Physical Design team to highlight issues and best practices. Your daily responsibilities include creating timing ECOs, developing scripts and methodologies for analysis, and performing deep analysis of timing paths to identify key issues. The role requires expertise in STA, noise, crosstalk, and OCV effects. You will utilize Perl and TCL for programming while managing circuit modeling with SPICE models. This position focuses on solving critical timing closure challenges within large high-performance SoC designs using sub-micron technologies.

Skills

STA Timing Closure Physical Design SPICE Perl TCL ECO OCV Crosstalk Netlist Tapeout Circuit Modeling

What you'll do

Execute the physical implementation of design partitions from netlist to tapeout for complex SoCs.
Analyze timing paths deeply to identify and resolve critical timing issues.
Develop and implement timing ECOs to ensure successful project tapeouts.
Create and maintain scripts and methodologies for analysis and automated runs.
Build and maintain the underlying timing infrastructure for the design process.
Collaborate with design teams to debug constraints and facilitate logic changes for timing improvement.
Develop technical documentation, guidelines, and specifications for physical design processes.

What we're looking for

Minimum Bachelor's degree with 0+ years industry experience.
Experience with Static Timing Analysis (STA).
Experience with noise, crosstalk, and/or OCV effects.
Familiarity with timing of large high-performance SoC designs in sub-micron technologies (preferred).
Experience with STA and methodologies for timing closure (preferred).
Familiarity with circuit modeling, including SPICE models, and worst-case corner selection (preferred).
Good programming skills with Perl and TCL (preferred).
Familiarity with ECO techniques and implementation (preferred).