SoC Physical Design Engineer, Power Delivery

Apple Inc

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Work type
On-site
Location
Austin, TX
Posted
104 days ago
Freshness
Confirmed live today

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Similar $203k
$137k $277k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $177,250–$229,100.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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TL;DR · SoC Physical Design Engineer, Power Delivery

The SoC Physical Design Engineer - Power Delivery will join a team responsible for completing partition place and route from netlist to tapeout, including automation tasks for Apple SOC. The role involves developing features and methodology solutions for a wide range of SOC partitions while ensuring a strong and DRC-clean power grid. Key responsibilities include collaborating multi-functionally with CAD, Physical Verification, Electrical analysis, and PnR teams. Candidates must possess technical expertise in automation for Physical Design, block execution, and scripting using TCL and Python. Required skills include ASIC integration knowledge such as floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration. The position requires proficiency with industry standard tools for PNR, Voltage Drop Analysis, STA, and Layout Verification to solve complex power delivery problems.

What you'll do

  • Complete partition place and route from netlist to tapeout for Apple SoCs.
  • Develop automation tasks for physical design using TCL and Python.
  • Design and maintain a DRC-clean power grid for various SoC partitions.
  • Create features and methodology solutions for wide-scale SoC partition use.
  • Perform voltage drop analysis and layout verification using industry-standard tools.
  • Manage floorplanning, clock distribution, and global signal planning for ASIC integration.
  • Execute block-level physical design tasks and automation scripts.

What we're looking for

  • Minimum of a BS degree and 10+ years of relevant industry experience.
  • Familiarity with ASIC integration, including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
  • Ability to write maintainable and reusable scripts/programs of medium complexity in TCL or Python.
  • Understanding of industry standard tools for PNR, Voltage Drop Analysis, STA, and Layout Verification.
  • Experience with automation for Physical Design, including block execution (preferred).
  • Experience with cross-functional collaboration with CAD, Physical Verification, Electrical analysis, and PNR teams (preferred).
  • Experience with tapeouts on the latest technology nodes (preferred).

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