SoC Physical Design Engineer, Power Delivery

What you'll do

• Execute partition place and route from netlist to tapeout for SoC designs.
• Develop automation tasks and tools using TCL and Python for physical design workflows.
• Design and maintain a DRC-clean power grid through cross-functional collaboration.
• Create methodology solutions and features applicable to a wide range of SoC partitions.
• Perform voltage drop analysis and layout verification to ensure an electrically robust power grid.
• Manage ASIC integration tasks including floorplanning, clock distribution, and hard IP integration.
• Develop maintainable and reusable scripts for complex physical design block executions.

What we're looking for

• Minimum of a Bachelor's degree and 10+ years of relevant industry experience.
• Experience with automation for Physical Design, including block execution using TCL and/or Python.
• Proficiency in writing maintainable and reusable scripts or programs of medium complexity in TCL or Python.
• Familiarity with ASIC integration aspects such as floorplanning, clock/power distribution, global signal planning, I/O planning, and hard IP integration.
• Understanding of industry standard tools for PNR, Voltage Drop Analysis, STA, and Layout Verification.
• Ability to collaborate cross-functionally with CAD, Physical Verification, Electrical analysis, and PnR teams.
• Experience with tapeouts on the latest technology nodes is preferred.