SoC Physical Design Engineer, STA/Timing

Apple Inc

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Work type: On-site
Location: Austin, TX
Posted: 16 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $210k

$146k most similar roles pay here $277k

This listing doesn't post a salary. Most similar roles pay $177,250–$241,750.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

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TL;DR · SoC Physical Design Engineer, STA/Timing

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As an SoC Physical Design Engineer, STA/Timing, you will be responsible for the physical implementation of design partitions from netlist to tapeout for highly complex SOCs using state of the art process technology. You will collaborate with design teams to debug constraints, facilitate logic changes to improve timing, and create timing ECOs for project tapeouts. Your daily work involves performing deep analysis of timing paths to identify key issues, creating documentation, and developing scripts and methodologies for analysis runs. The role requires expertise in large design STA and timing closure within sub-micron technologies. You will utilize Perl and TCL for scripting while managing complexities such as noise, crosstalk, OCV effects, circuit modeling with SPICE models, and worst-case corner selection to ensure successful tapeout of high-performance hardware components.

Skills

STA Timing Closure Physical Design Perl TCL ECO SPICE Crosstalk OCV Circuit Modeling Netlist Tapeout

What you'll do

Execute the physical implementation of design partitions from netlist to tapeout for complex SoCs.
Perform deep analysis of timing paths to identify and resolve critical issues.
Develop timing ECOs to ensure successful project tapeouts.
Create and maintain scripts and methodologies for automated analysis and runs.
Implement timing infrastructure to support the physical design flow.
Collaborate with design teams to debug constraints and facilitate logic changes for improved timing.
Develop documentation, guidelines, and specifications for the physical design process.

What we're looking for

Minimum BS degree and 3+ years of relevant industry experience.
Experience with large design STA and/or Timing Closure.
Programming skills in Perl and TCL.
Hands-on experience in STA (preferred).
Familiarity with timing of large high-performance SoC designs in sub-micron technologies (preferred).
Proficiency in STA, timing closure methodologies, and understanding of noise, crosstalk, and OCV effects (preferred).
Familiarity with circuit modeling, including SPICE models, and worst-case corner selection (preferred).
Familiarity with ECO techniques and implementation (preferred).

GPU Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 16 days ago

STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting EDA Tools VLSI CMOS ECO Tapeout Digital Logic Design

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