SoC Physical Design Engineer, PnR

As an SoC Physical Design Engineer, PnR, you will join a technical team focused on high-performance and low-power chip design. You will be responsible for all aspects of physical design implementation from RTL2GDS, including floorplanning, bump/RDL, static timing analysis, physical verification, EMIR, and sign-off. The role involves collaborating with cross-functional teams to develop efficient chip and IP physical architectures while establishing best-known methods and guidelines to streamline workflows. You will serve as the primary technical contact for your area, solving complex timing closure issues, area optimization, and power optimization challenges. Required skills include experience with deep submicron technology, large SOC designs exceeding 20M gates at frequencies over 1GHz, and proficiency in industry standard tools. Your work addresses critical physical design constraints early in the cycle to meet stringent schedule and die size requirements.