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Active Keyword: SR ASIC Design Engineer Remove filter Clear all

12 of up to 20 (filtered)

Senior Staff ASIC Design Engineer

Amd

San Jose, CA 7 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday Posted this week High trust Above market
Verilog System Verilog DFT ATPG RTL Design UVM OVM Python Tcl Perl Shell Synopsys DC Compiler PrimeTime Cadence Virtuoso VCS Static Timing Analysis FPGA HBM PCIe SerDes
Hybrid
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Senior ASIC Design Verification Engineer

SpaceX

Austin, TX 59 days ago
Actively hiring Confirmed live 2 days ago Low trust
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Redmond, WA 59 days ago $165,000–$260,000
Actively hiring Confirmed live 2 days ago Low trust Above market
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Palo Alto, CA 59 days ago $175,000–$280,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Test Bench Development Object-Oriented Programming Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Irvine, CA 59 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification test bench development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Scripting Functional Coverage
5+ yrs exp
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Senior ASIC Design Verification Engineer

Amazon Inc

Sunnyvale, CA +1 78 days ago $159,200–$215,300
Actively hiring Confirmed live 2 days ago High trust Above market
UVM C++ C System C DPI-C Formal Verification Matlab RTL FPGA Emulation Digital Verification ASIC Scripting CMOS
7+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA 108 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis (STA) EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Sunnyvale, CA 108 days ago $175,000–$280,000
Actively hiring Confirmed live 2 days ago Low trust Above market
ASIC Physical Design RTL2GDSII STA EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis Electromigration
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Austin, TX 108 days ago
Actively hiring Confirmed live 2 days ago Low trust
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route DFT Scan MBIST LBIST FinFET CMOS Python TCL Perl Bash Makefile EDA Tools
5+ yrs exp
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Senior ASIC Design Engineer, NoC & AXI Interconnect

Amd

Santa Clara, CA 115 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday High trust Above market
NoC AXI ACE APB SystemVerilog Verilog RTL Design VCS Python Perl Shell Scripting ASIC Design Buffer Management Post-silicon Bring-up
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Senior ASIC Design Engineer, Ethernet Switch & High-Speed I/O

Amd

Santa Clara, CA 115 days ago $200,000–$300,000
Actively hiring Confirmed live 2 days ago High trust Above market
RTL Design SystemVerilog Verilog Ethernet SerDes VCS Python Perl Shell Scripting ASIC Design Switch Fabric Queue Management High-speed I/O Post-silicon Bring-up
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Senior ASIC Design Engineer

SpaceX

Hawthorne, CA 162 days ago $160,000–$225,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC FPGA Verilog System Verilog RTL Python TCL AXI AHB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Synthesis Timing Closure Formality
5+ yrs exp
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