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Active Keyword: SR ASIC Design Engineer Remove filter Clear all

14 of up to 20 (filtered)

Senior ASIC Design Engineer

SpaceX

Palo Alto, CA +3 18 days ago $175,000–$280,000
Actively hiring Confirmed live today Trusted Above market
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp
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Senior ASIC Design Engineer

SpaceX

Irvine, CA +3 27 days ago $165,000–$265,000
Actively hiring Confirmed live today Trusted Competitive pay
Verilog System Verilog RTL Design ASIC SoC Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp
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Senior ASIC Design Engineer

SpaceX

Redmond, WA +3 27 days ago $165,000–$270,000
Actively hiring Confirmed live yesterday Trusted Above market
RTL Design Verilog System Verilog ASIC SoC Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems
5+ yrs exp
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Senior ASIC Design Engineer

SpaceX

Austin, TX +3 27 days ago
Actively hiring Confirmed live today Low trust
Verilog System Verilog RTL Design ASIC SoC Synthesis Timing Closure AXI AHB Python HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems Formality Check Silicon Bring-up
5+ yrs exp
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Senior Staff ASIC Design Engineer

Amd

San Jose, CA 53 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
Verilog System Verilog UVM Python Tcl Perl Shell RTL Design DFT Static Timing Analysis Synthesis place-and-route FPGA PCIe Serdes HBM Synopsys DC Compiler Primetime VCS Cadence Virtuoso
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Senior ASIC Design Verification Engineer

SpaceX

Austin, TX 105 days ago
Actively hiring Confirmed live today Low trust
ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models Scripting Digital Design
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Redmond, WA 105 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage Test Plans Scripting
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Palo Alto, CA 105 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage
5+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Irvine, CA 105 days ago $165,000–$260,000
Actively hiring Confirmed live today Low trust Competitive pay
ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage Test Plans Scripting
5+ yrs exp
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Senior ASIC Design Verification Engineer

Amazon Inc

Sunnyvale, CA +1 124 days ago $185,200–$250,000
Actively hiring Confirmed live today Low trust Above market
UVM C/C++ Formal Verification System C DPI-C Matlab RTL FPGA Emulation Scripting DSP CMOS
7+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA +2 154 days ago $165,000–$260,000
Actively hiring Confirmed live today Low trust Competitive pay
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Palo Alto, CA +3 154 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Austin, TX +2 154 days ago
Actively hiring Confirmed live today Low trust
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route Physical Verification Electromigration Voltage Drop Logic Equivalency FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools
5+ yrs exp
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Senior ASIC Design Engineer, NoC & AXI Interconnect

Amd

Santa Clara, CA 161 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday High trust Above market
ASIC Design SystemVerilog Verilog RTL Design Network-on-Chip NoC AXI ACE APB VCS Python Perl Shell Scripting Post-silicon Bring-up Buffer Management
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