Senior ASIC Design Engineer, NoC & AXI Interconnect

Amd

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $200,000–$300,000 / yr
Posted: 115 days ago
Freshness: Confirmed live yesterday
Closes: May 19, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $250k

$135k most similar roles pay here $318k

This role pays more than 89% of similar roles. Most pay $175,000–$223,000 — the shaded band above. At the midpoint, this role pays about $250k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

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View all roles at Amd

At a glance

TL;DR · Senior ASIC Design Engineer, NoC & AXI Interconnect

Role Posting Log in to save

As a SR ASIC Design Engineer - NoC & AXI Interconnect on the NTSG ASIC Design Team, you will contribute to the front-end design and integration of high-performance network chips, specifically AINIC and DPU. You will work closely with architecture, IP design, physical design teams, and product engineers to achieve first-pass silicon success while providing post-silicon bring-up support and yield learning. Your daily responsibilities include Network-on-Chip design and integration, as well as the design and verification of AXI, ACE, and APB interfaces alongside queuing system implementation and buffer management. To succeed in this role, you must possess expertise in SystemVerilog and Verilog RTL design, experience with VCS simulation tools, and proficiency in Perl, Python, or Shell scripting to solve complex problems within the high-performance networking domain.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

NoC AXI ACE APB SystemVerilog Verilog RTL Design VCS Python Perl Shell Scripting ASIC Design Buffer Management Post-silicon Bring-up

What you'll do

Design and integrate Network-on-Chip (NoC) architectures for high-performance network chips.
Design and verify AXI, ACE, and APB interfaces.
Design and implement queuing systems and manage buffer management.
Work with architecture, IP, and physical design teams to ensure first-pass silicon success.
Provide post-silicon bring-up support and contribute to yield learning.
Develop RTL designs using SystemVerilog or Verilog.
Utilize VCS simulation tools and write Perl, Python, or Shell scripts for automation.

What we're looking for

Bachelor's or Master's degree in computer engineering or Electrical Engineering.
Experience with SystemVerilog and Verilog RTL design.
Proficiency in VCS simulation tools and Perl, Python, or Shell scripting.
Understanding of Network-on-Chip (NoC) architecture, protocols, and design.
Experience with AXI, ACE, and APB interface design and verification.
Knowledge of queuing system design and buffer management.
Strong communication and problem-solving skills.
High level of accuracy and attention to detail.

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