Senior ASIC Design Engineer, NoC & AXI Interconnect

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$200,000–$300,000 / yr
Posted
161 days ago
Freshness
Confirmed live today
Closes
May 19, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $250k
$132k $318k
below market most similar roles pay here above market

This role pays more than 88% of similar roles. Most pay $168,500–$223,000 — the blue band above. At the midpoint, this role pays about $250k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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View all roles at Amd

At a glance

TL;DR · Senior ASIC Design Engineer, NoC & AXI Interconnect

Role Posting Log in to save

As a SR ASIC Design Engineer - NoC & AXI Interconnect, you will join the NTSG ASIC Design Team to contribute to the front-end design and integration of high-performance network chips, specifically AINIC and DPU. You will work closely with architecture, IP design, physical design, and product engineering teams to achieve first-pass silicon success. Your daily responsibilities include Network-on-Chip design and integration, queuing system design and implementation, and AXI, ACE, and APB interface design and verification. You will also provide post-silicon bring-up support and yield learning. The role requires proficiency in SystemVerilog, Verilog RTL design, and the VCS simulation tool, along with Perl, Python, or Shell scripting. You must possess a deep understanding of NoC architecture, protocols, and buffer management.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

ASIC Design SystemVerilog Verilog RTL Design Network-on-Chip NoC AXI ACE APB VCS Python Perl Shell Scripting Post-silicon Bring-up Buffer Management

What you'll do

  • Design and integrate Network-on-Chip (NoC) components for high-performance network chips.
  • Design and verify AXI, ACE, and APB interfaces.
  • Design and implement queuing systems and buffer management.
  • Work with architecture, IP, and physical design teams to achieve first-pass silicon success.
  • Provide post-silicon bring-up support and yield learning.
  • Develop RTL designs using SystemVerilog and Verilog.
  • Utilize VCS simulation tools and Perl, Python, or Shell scripting for design tasks.

What we're looking for

  • Bachelor's or Master's degree in computer engineering or Electrical Engineering.
  • Experience with VCS simulation tool, Perl/Python/Shell scripting, and SystemVerilog/Verilog RTL design (preferred).
  • Experience with AXI, ACE, and APB interface design and verification (preferred).
  • Understanding of Network-on-Chip (NoC) architecture, protocols, and design (preferred).
  • Knowledge of queuing system design and buffer management (preferred).
  • Strong communication and problem-solving skills.
  • Ability to work with high accuracy and attention to detail.

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