Senior Staff ASIC Design Engineer

Amd

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Salary: $200,000–$300,000 / yr
Posted: 7 days ago
Freshness: Confirmed live yesterday
Closes: Sep 4, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k

This role $250k

$146k most similar roles pay here $316k

This role pays more than 87% of similar roles. Most pay $177,250–$227,300 — the shaded band above. At the midpoint, this role pays about $250k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Senior Staff ASIC Design Engineer

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As a Sr. Staff ASIC Design Engineer on the front-end design and integration team, you will develop next-generation graphics and compute technologies while collaborating with Architecture, IP Design, Physical Design, and Product Engineering teams to achieve first-pass silicon success. Your daily responsibilities include implementing and verifying DFT architecture and features, performing scan insertion, generating ATPG patterns, conducting gate-level simulation verification, and analyzing test coverage and cost reduction. You will also provide post-silicon support for bring-up and yield learning. The role requires expertise in Verilog, SystemVerilog, and UVM/OVM, along with experience in RTL design for Digital and Analog blocks involving HBM, D2D, Serdes, and PCIe protocols. Technical proficiency includes VLSI design, Static Timing Analysis, and scripting in Perl, Tcl, Shell, or Python to support the development of high-quality silicon products.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

Verilog System Verilog DFT ATPG RTL Design UVM OVM Python Tcl Perl Shell Synopsys DC Compiler PrimeTime Cadence Virtuoso VCS Static Timing Analysis FPGA HBM PCIe SerDes

What you'll do

Implement and verify DFT architecture and features.
Perform scan insertion and generate ATPG patterns.
Verify ATPG patterns using gate-level simulation.
Analyze test coverage and identify opportunities for test cost reduction.
Provide post-silicon support to ensure successful bring-up and accelerate yield learning.
Develop RTL designs for digital and analog blocks using Verilog or SystemVerilog.

What we're looking for

Bachelor's or master's degree in computer engineering, Electrical Engineering, or a related field.
Strong communication and problem-solving skills.
Experience with RTL design implementation of Digital/Analog blocks using Verilog/System Verilog (preferred).
Knowledge of VLSI design, Design Automation, and IC design (preferred).
Knowledge of Physical Design and Static Timing Analysis (preferred).
Basic knowledge of EDA Tools such as Synopsys DC Compiler, Primetime, VCS, or Cadence Virtuoso (preferred).
Experience with UVM/OVM, Verilog, System Verilog test benches, and simulation tools (preferred).
Proficiency in Perl, Tcl, Shell, Python, or other scripting languages (preferred).

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