Senior Staff ASIC Design Engineer

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$200,000–$300,000 / yr
Posted
53 days ago
Freshness
Confirmed live today
Closes
Sep 4, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k
This role $250k
$135k $318k
below market most similar roles pay here above market

This role pays more than 89% of similar roles. Most pay $177,250–$225,300 — the blue band above. At the midpoint, this role pays about $250k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · Senior Staff ASIC Design Engineer

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The Sr. Staff ASIC Design Engineer joins the FPGA Product and Platform development team within the Adaptive & Embedded Computing Group. This role involves technical execution of device programs from definition to productization, specifically supporting IP development for silicon implementation and first-time-right software solutions. Key responsibilities include designing and implementing RTL for complex digital and mixed-signal blocks, supporting physical design activities like synthesis, DFT, and Static Timing Analysis, and collaborating with functional verification teams. The position requires proficiency in Verilog, SystemVerilog, and UVM/OVM, along with experience in protocols such as HBM, D2D, Serdes, and PCIe. Candidates must utilize scripting languages including Perl, Tcl, Shell, and Python, while leveraging EDA tools like Synopsys DC Compiler, Primetime, VCS, and Cadence Virtuoso.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

Verilog System Verilog UVM Python Tcl Perl Shell RTL Design DFT Static Timing Analysis Synthesis place-and-route FPGA PCIe Serdes HBM Synopsys DC Compiler Primetime VCS Cadence Virtuoso

What you'll do

  • Design and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.
  • Participate in all design flow stages from initial RTL development through GDS implementation.
  • Support physical design activities including synthesis, DFT implementation, place-and-route, and Static Timing Analysis.
  • Collaborate with Functional Verification teams to support block-level verification using System Verilog and UVM.
  • Develop and maintain design automation tools and flows using Perl, Tcl, Shell, and Python.
  • Resolve technical issues and ensure project milestones are met through regular communication with global project teams.

What we're looking for

  • Bachelor's or master's degree in computer engineering, electrical engineering, or a related field.
  • Design and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.
  • Support physical design activities including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
  • Utilize scripting languages such as Perl, Tcl, Shell, and Python to maintain design automation flows and develop new tools.
  • Collaborate with Functional Verification teams using constrained-random and directed test environments based on System Verilog and UVM.
  • Experience with HBM, D2D, Serdes, and PCIe-like protocols (preferred).
  • Basic knowledge of EDA tools like Synopsys DC Compiler, Primetime, VCS, and Cadence Virtuoso (preferred).
  • Basic understanding of FPGA architecture and customer usage model (preferred).

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