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Verilog VHDL SystemVerilog SOC Architecture DRAM Interface Design Synthesis Formal Verification Timing Closure Signal Integrity Physical Implementation HDL +6 more Show less

Physical Design Place and Route Static Timing Analysis Physical Verification Formal Equivalency Verification IR-Drop Electromigration TCL Python Synopsys Fusion Compiler PrimeClosure Primetime Formality VCLP Star-RC Redhawk SC Cadence Innovus Siemens Calibre ASIC SOC +15 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting SoC Circuit Design +5 more Show less

Python Claude Innovus ICC2 Calibre Tcl Docker OpenAI API Pinecone Weaviate RAG LLM MLPD STA DRC EDA Tools Vector Databases +12 more Show less

UVM SystemVerilog C++ Python Ruby Perl Verilog VHDL Agile Makefiles FPGA Emulation Assertion Functional Coverage Co-Pilot Scripting +11 more Show less

ASIC Physical Design Floorplanning Power Planning Clock Tree Synthesis Static Timing Analysis Signal Integrity RC Extraction DFT UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime +14 more Show less

Silicon Photonics SKILL DRC LVS Verilog-A Ansys Lumerical ZeMax MATLAB Python FDTD FDE EME DWDM Co-packaged Optics (CPO) +9 more Show less

Electrical Engineering Data Center Design Power Generation Grounding Liquid Cooling Commissioning Technical Writing Contract Administration MSDS lockout/tag out High-Density Compute +6 more Show less

Electrical Engineering Data Center Design Power Generation Grounding Liquid Cooling Commissioning Technical Writing MSDS lockout/tag out Contract Administration High-Density Compute +6 more Show less

Analog Circuit Design High Voltage DC Power Systems SPICE Cadence Mentor Graphics Altium Prototyping Magnetics High Speed Design Spectrum Analyzers Oscilloscopes R&D +7 more Show less

ASIC SoC Physical Design RTL-to-GDSII Synthesis Place & Route STA Timing Closure Power Optimization TCL Python Synopsys Cadence PPA EM/IR Advanced Nodes +10 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models +9 more Show less

UVM SystemVerilog OVM AMS RTL SoC Python MATLAB C C++ Ruby Perl Azure DFT Simulation Verification Methodology Scripting Data Analysis AI Tools +14 more Show less

ASIC FPGA Verilog System Verilog RTL Python TCL AXI AHB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Synthesis Timing Closure +12 more Show less