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16 of up to 20 (filtered)

Principal Design Verification Engineer, Formal

Microsoft

4 days ago $142,800–$274,800
Actively hiring Confirmed live today Posted this week Trusted Competitive pay
Formal Verification System Verilog UVM Python Fabric Interconnects CHI AMBA PCIe CXL Assertions Coverage-Driven Verification Simulation Root-Cause Analysis AI-assisted tools
8+ yrs exp Hybrid

Principal IC Design Engineer, Analog

Medtronic

Mounds View, MN +1 5 days ago $140,000–$210,000
Actively hiring Confirmed live today Posted this week High trust Below market
Mixed-Signal IC Design Cadence EDA Spectre ADE Layout Python LabView AMS PVT Variation Parasitic Extraction Signal Integrity Subthreshold Design Formal Verification Simulation Testbenches Characterization
7+ yrs exp

Principal Physical Design Engineer

Microsoft

7 days ago $165,600–$296,400
Actively hiring Confirmed live today Posted this week High trust Above market
Physical Design Silicon Design Synthesis Place and Route Clock Construction CTS Timing Signoff Physical Verification EMIR Formal Equivalence Low Power Verification RTL to GDS PPA Floorplanning Extraction Tape-out
10+ yrs exp Hybrid

Principal Design Verification Engineer

Microsoft

14 days ago $142,800–$274,800
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog UVM C++ Python Verilog VHDL Ruby Perl Agile Hardware Emulation FPGA Makefiles Scripting Post-Silicon Validation Pre-Silicon Functional Verification
8+ yrs exp Hybrid

Principal Design Engineer, Interactive Graphics

Microsoft

20 days ago $142,800–$274,800
Actively hiring Confirmed live today High trust Competitive pay
JavaScript TypeScript WebGL WebGPU GLSL WGSL Three.js React Three Fiber GSAP Motion Shaders Real-time Rendering Component Architecture GPU Profiling Accessibility Human Computer Interaction
6+ yrs exp Hybrid

Principal CPU Physical Design Engineer

Qualcomm

San Diego, CA 35 days ago $216,600–$325,000
Actively hiring Confirmed live today High trust Above market
ASIC SoC Physical Design RTL-to-GDSII Synthesis Place & Route STA Signoff Timing Closure Power Optimization TCL Python Synopsys Cadence PPA EM/IR Power Integrity
10+ yrs exp

Physical Design Engineer

Qualcomm

San Diego, CA +2 40 days ago $123,100–$250,000
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Design Physical Design Place and Route Static Timing Analysis Clock Tree Synthesis Floorplanning Power Planning Signal Integrity Analysis Physical Verification DFT Low Power Design UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime RC Extraction ECO Implementation
4+ yrs exp

AI-Driven ASIC Physical Design Principal Engineer

Cisco

San Jose, CA 64 days ago
Actively hiring Confirmed live today High trust
Python ASIC EDA Tools Innovus ICC2 Calibre Tcl Docker RAG LLM Pinecone Weaviate OpenAI API GPT-4o MLPD RTL2GDSII Tempus Primetime Redhawk Voltus Pegasus
10+ yrs exp Hybrid

Principal Photonics IC Design Engineer

Nvidia

Santa Clara, CA 76 days ago $232,000–$368,000
Actively hiring Confirmed live today High trust Above market
Silicon Photonics SKILL Scripting DRC LVS Tapeout Python Verilog-A MATLAB Ansys Lumerical ZeMax FDTD FDE EME DWDM Co-packaged Optics Mixed-Signal Design
8+ yrs exp

Senior Principal Electrical Engineer, Data Center Design and Innovation

Oracle

144 days ago $146,300–$306,400
Actively hiring Confirmed live today High trust Above market
Data Center Design Thermal Management Cooling Technologies High-Performance Computing HPC Infrastructure Design Thermal Simulation Heat Rejection Systems Airflow Strategies Hardware Development Quality Assurance Basis of Design Oracle Cloud Infrastructure OCI
6+ yrs exp

Principal Design Verification Engineer

SpaceX

Palo Alto, CA +4 159 days ago $210,000–$355,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC FPGA UVM OVM VMM Python RTL Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp

Principal Design Verification Engineer

SpaceX

Irvine, CA +3 159 days ago $210,000–$335,000
Actively hiring Confirmed live today Low trust Above market
ASIC FPGA UVM OVM VMM Python RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp

Principal Design Verification Engineer

SpaceX

Redmond, WA +3 159 days ago $210,000–$335,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC FPGA UVM OVM VMM Python RTL Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp

Principal Design Verification Engineer

SpaceX

Austin, TX +3 159 days ago
Actively hiring Confirmed live today Low trust
ASIC FPGA UVM OVM VMM Python RTL Pre-silicon Verification Post-silicon Validation Chip Bring-up Constrained Random Verification Object-Oriented Programming Test Bench Development Coverage Models Scripting Digital Design
10+ yrs exp

Principal Quantum Design Verification Engineer

Microsoft

167 days ago $142,800–$274,800
Actively hiring Confirmed live today High trust Competitive pay
SystemVerilog UVM OVM Python C C++ MATLAB Ruby Perl AMS RTL DFT SoC Azure Simulation Validation Characterization
8+ yrs exp Hybrid