Principal Quantum Design Verification Engineer

Microsoft

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Redmond, WA
Salary
$142,800–$274,800 / yr
Posted
121 days ago
Freshness
Confirmed live 2 days ago
Closes
Nov 9, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $209k
$124k most similar roles pay here $291k

This role pays more than 69% of similar roles. Most pay $168,425–$216,250 — the shaded band above. At the midpoint, this role pays about $209k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 598 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 586 roles with salary data.

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At a glance

TL;DR · Principal Quantum Design Verification Engineer

As a Principal Quantum Design Verification Engineer on the Quantum 1st Party Hardware System-on-Chip team, you will lead the development of quantum SoC verification infrastructure. You will define pre-silicon simulation plans and post-silicon validation and characterization plans for SoC and IP blocks while coordinating staff and external vendors to ensure high-quality designs. Your daily work involves owning verification environments, managing bug-tracking systems, and creating test plans for digital and analog components, including Analog Mixed-Signal simulation models. You will collaborate with architecture, physical design, and DFT teams to bring hardware into production for scalable quantum systems. Required skills include expertise in SystemVerilog, UVM, or OVM, along with proficiency in MATLAB and scripting languages like Python, Ruby, or Perl. The role addresses the technical challenge of developing reliable hardware for quantum information technology.

What you'll do

  • Own verification environments and tests for IP and SoC designs across pre- and post-layout RTL and netlists.
  • Define pre-silicon simulation plans and post-silicon validation/characterization plans for SoC and IP blocks.
  • Coordinate contingent staff and external vendors to ensure deliverables meet technical specifications and schedules.
  • Manage databases, bug-tracking systems, and project milestones for SoC and IP repositories.
  • Create test plans for digital and analog components, including the development of Analog Mixed-Signal (AMS) simulation models.
  • Collaborate with Design For Test teams to verify and validate DFT features.
  • Drive continuous improvement of design verification processes and methodologies for at-scale execution.

What we're looking for

  • A Doctorate in Physics or Engineering with 3+ years of experience, a Master's with 6+ years, or a Bachelor's with 8+ years.
  • Ability to pass Microsoft Cloud Background Check and meet export control requirements (ITAR/EAR).
  • Proof of citizenship or U.S. permanent residency for access to export-controlled information.
  • Proficiency in Universal Verification Methodology (UVM), Open Verification Methodology (OVM), and SystemVerilog.
  • Experience with Analog Mixed-Signal (AMS) verification, including modeling, simulation, and silicon characterization.
  • Proficiency in MATLAB for complex modeling and visualization.
  • Proficiency in scripting languages such as Python, Ruby, or Perl for automation and data analysis.
  • Master's Degree in Physics, Engineering, or related field AND 6+ years.

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