Browse tech roles

ASIC Design RTL Design Verilog VHDL Synthesis Timing Analysis CHI CXL PCI-E PERL CAD Tools Hardware-managed Coherency System Level Caches Protocol Bridges Asynchronous Interfaces +10 more Show less

DDR LPDDR JEDEC Network-on-Chip RAS IBIS IBIS-AMI C SystemVerilog Verilog JTAG Oscilloscope Signal Integrity Power Integrity LLM PCB Layout Hardware Debug +12 more Show less

DDR Memory Tuning Signal Integrity Oscilloscopes Schematic Capture Board Design C C++ Java Python Perl Windows OS Linux Firmware +8 more Show less

System Verilog Verilog UVM Python C++ ASIC Verification RTL Computer Architecture Testbench Development Regression Triage Coverage Closure Debug Caches Coherency Pipelines Arbitration Interconnect Networks Algorithms Data Structures +14 more Show less

LPDDR DRAM DDR6 JEDEC SoC PHY PMIC Firmware SPD System Integration Validation Telemetry Clocking Thermal Design Packaging Protocols Interoperability +12 more Show less

UVM System Verilog Formal Verification Python PCIe CXL AMBA CHI JEDEC Memory Controller IP Verification Generative AI Simulation SVTB +9 more Show less

DDR5 LPDDR5x Post-Silicon Validation First-Silicon Bring-up Root-Cause Analysis Memory Subsystems Firmware Software Pre-silicon Validation Lab Equipment AI Automation +7 more Show less

SoC DRAM Memory Subsystem Silicon Validation DDR PHY Design DFT Design for Test NPI Memory Controller High-Speed IO Calibration Training Mechanisms +8 more Show less

SoC DRAM Memory Subsystem Silicon Validation DDR PHY Design DFT NPI Memory Controller High-Speed IO Calibration Training Mechanisms +7 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design +4 more Show less

ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture +12 more Show less

SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification Constrained-Random Verification Coverage-Driven Verification LPDDR DDR HBM JEDEC UPF AXI APB AHB DFI RTL Simulation +15 more Show less

Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture +9 more Show less

SoC Architecture Memory Subsystems DDR LPDDR HBM Cache Subsystems JEDEC CHI ACE AXI Arm Architecture Android Cache Coherence Protocols Bus Protocols +9 more Show less

HBM GDDR DRAM ASIC VLSI Mixed Signal Design Signal Integrity Linux Scripting Data Analysis Hardware Design Board Design ATE High-Performance Computing Artificial Intelligence +10 more Show less

DDR Memory Tuning Mixed Signal Digital Design Embedded Systems Signal Integrity Schematic Capture Board Design C C++ Java Python Perl Linux Windows OS Oscilloscopes High-Performance Computing Firmware +12 more Show less