SoC Architect, Memory Subsystem

Samsung Electronics

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CAAustin, TX
Salary
$124,000–$208,400 / yr
Employment
Full-time
Posted
51 days ago
Freshness
Confirmed live today
Closes
Dec 31, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $224k
This role $166k
$106k $296k
below market most similar roles pay here above market

This role pays less than 85% of similar roles. Most pay $192,362–$254,750 — the blue band above. At the midpoint, this role pays about $166k versus about $224k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 86 open roles on FindRole.

Listed pay typically runs $106,000–$179,090 across 79 roles with salary data.

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At a glance

TL;DR · SoC Architect, Memory Subsystem

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As a SoC Architect, Memory Subsystem, you will join the System IP & SoC Architecture team to shape premium chipsets by defining innovative memory and cache subsystems. You will identify, propose, and deliver new architectures for mobile platforms, creating detailed specifications for memory interfaces, controllers, and caches. Your daily work involves analyzing PPA trade-offs to optimize performance, power, and area while collaborating with software and hardware teams. You must possess expertise in memory hierarchies, DDR, LPDDR, HBM, and JEDEC standards. The role requires deep knowledge of cache policies, scheduling, and bandwidth management. Preferred skills include experience with cache coherence protocols like CHI, ACE, and AXI, as well as the Arm architecture and Android ecosystem, to solve complex problems in gaming and computational photography.

Skills

SoC Architecture Memory Subsystems DDR LPDDR HBM Cache Subsystems JEDEC CHI ACE AXI Arm Architecture Android Cache Coherence Protocols Bus Protocols

What you'll do

  • Identify and deliver new SoC memory architectures and features for premium mobile platforms.
  • Create detailed designs and specifications for memory interfaces, controllers, and caches.
  • Analyze PPA trade-offs to optimize memory subsystem performance, power consumption, and area utilization.
  • Develop and maintain detailed documentation for architecture, implementation, and verification plans.
  • Recommend and integrate emerging memory technologies into SoC designs.
  • Ensure memory subsystem designs meet system requirements through integration with software and hardware teams.

What we're looking for

  • Must have 4+ years of experience with a Bachelor’s Degree in Computer Science/Engineering.
  • Must have 2+ years of experience with a Master’s Degree in Computer Science/Engineering.
  • Must have a PhD in Computer Science/Engineering.
  • Must have experience designing and developing complex digital systems and SoC memory architectures.
  • Must have a strong understanding of memory hierarchies, memory interfaces (e.g., DDR, LPDDR, HBM), and memory controllers.
  • Must have detailed knowledge of cache subsystems, including caching policies and latency/bandwidth tradeoffs.
  • Must have knowledge of memory scheduling, bandwidth management, and latency optimization.
  • Must have high familiarity with existing and emerging JEDEC memory standards.
  • Must have strong written and verbal communication skills.
  • Experience with cache coherence protocols and bus protocols (e.g., CHI, ACE, AXI) is a plus (preferred).
  • Experience with the Android ecosystem and analysis tools is a plus (preferred).
  • Experience with Arm architecture and ecosystem is a plus (preferred).
  • Must be authorized to access information subject to U.S. export control laws.

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