Principal Memory Subsystem Architect

Amd

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Georgia, GA
Salary
$176,560–$264,840 / yr
Posted
8 days ago
Freshness
Confirmed live yesterday
Closes
Oct 3, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $221k
This role $221k
$163k $290k
below market most similar roles pay here above market

This role pays less than 52% of similar roles. Most pay $185,500–$257,125 — the blue band above. At the midpoint, this role pays about $221k versus about $221k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 510 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 510 roles with salary data.

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At a glance

TL;DR · Principal Memory Subsystem Architect

The Principal Memory Subsystem Architect joins the Memory Standards Architecture team to own the architecture strategy for low-power DRAM and advanced memory-buffer technologies. This role involves defining multi-generation LPDDR and DRAM-buffer roadmaps, leading technical positions for LPDDR devices, DDR6 registered clock drivers, and LPDDR6 in-package buffers, and representing the company in JEDEC. The architect will define requirements for partitioning, topology, protocols, clocking, training, performance, power, telemetry, reliability, security, and interoperability. Key responsibilities include coordinating DRAM behavior with controllers, PHYs, SoCs, and firmware while aligning DRAM vendors and suppliers on qualification plans and adoption risks. The position requires expertise in memory-technology, system-level tradeoffs, and industry standards to deliver implementation specifications for architecture, SPD, configuration, authentication, attestation, and thermal design.

What you'll do

  • Define and own the multi-generation LPDDR and DRAM-buffer architecture strategy and roadmap across all business units.
  • Serve as the company-wide technical authority for LPDDR devices, registered clock drivers, and advanced DRAM-buffer technologies.
  • Represent AMD in JEDEC and other standards bodies to lead technical proposals, negotiations, and consensus building.
  • Define architectural requirements for LPDDR devices, including topology, protocols, clocking, power, reliability, and security.
  • Coordinate DRAM and buffer behavior with controller, PHY, SoC, package, firmware, and platform requirements.
  • Deliver detailed implementation specifications for SPD, configuration, authentication, thermal design, and fault handling.
  • Align DRAM vendors and component suppliers on roadmaps, qualification plans, and interoperability milestones.
  • Lead cross-functional workgroups to resolve technical tradeoffs and provide reusable solutions and launch-readiness support.

What we're looking for

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field required.
  • Master’s degree or PhD preferred.
  • Recognized expertise in memory technology, specifically LPDDR and DDR.
  • Experience defining architecture for LPDDR devices, DDR6 registered clock drivers, and in-package buffers.
  • Ability to lead technical positions and consensus building within JEDEC and other standards organizations.
  • Experience coordinating DRAM and buffer behavior with controller, PHY, SoC, package, and firmware requirements.
  • Ability to align internal teams and external vendors on roadmaps, qualification plans, and interoperability.
  • Proven ability to communicate complex technical decisions and resolve competing priorities across organizational boundaries.

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