Senior Staff Product Application Engineer, Memory Subsystems

What you'll do

• Root-cause escalated memory failures on real systems and drive fixes across DRAM, board, controller IP, and firmware.
• Review next-generation memory and Network-on-Chip architecture designs to identify and fix defects before silicon production.
• Author customer-facing documentation including product guides, datasheets, tutorials, and layout guidance.
• Perform DRAM signal integrity, power integrity, and timing measurements using IBIS models and channel simulations.
• Create C-based memory tests and tooling to stress and characterize specific failure modes on hardware.
• Translate system-level challenges into product roadmap decisions regarding supported configurations and data rates.
• Use AI and ML tools to summarize large test datasets and identify design gaps in engineering workflows.

What we're looking for

• Provide technical point of contact for escalated memory cases from early design-in through production support.
• Root-cause system memory failures across DRAM, board, controller IP, calibration firmware, and silicon.
• Author customer-facing memory documentation including product guides, datasheets, and layout guidance.
• Review memory and Network-on-Chip architecture for next-generation silicon to identify bugs and gaps.
• Perform DRAM SI/PI and timing measurements using IBIS/IBIS-AMI models and PCB layout knowledge.
• Write targeted memory tests in C to stress and characterize failure modes on real hardware.
• Extensive hands-on experience with memory subsystems across multiple DRAM generations (preferred).
• Expertise in DDR/LPDDR generations, JEDEC specifications, and module variants (preferred).
• Deep knowledge of memory controller and PHY architecture, including command scheduling and RAS features (preferred).
• Proven root cause of system-level failures using oscilloscopes, signal generators, and logic analyzers (preferred).
• Experience working directly with strategic customers to influence product and roadmap decisions (preferred).
• Demonstrated use of AI/LLM/ML tools in engineering workflows (preferred).
• Strong C skills and ability to read SystemVerilog/Verilog RTL to identify implementation bugs (preferred).