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20 of up to 20 (filtered)

Senior Memory Post Silicon Qualification Engineer

Nvidia

Santa Clara, CA 2 days ago $168,000–$264,500
Actively hiring Confirmed live yesterday Posted this week High trust Above market
GDDR LPDDR HBM Memory Characterization PHY SI/PI Firmware Oscilloscope Protocol Analyzers RAG Data Analysis Timing Margin Analysis
10+ yrs exp

Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Irvine, CA +3 3 days ago $165,000–$265,000
Actively hiring Confirmed live yesterday Posted this week High trust Competitive pay
RTL Verilog System Verilog ASIC SoC AXI AHB Python EDA Tools HDL Simulators Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up

Silicon Photonics PIC Layout Engineer

Broadcom

San Jose, CA 3 days ago $101,000–$162,000
Actively hiring Confirmed live yesterday Posted this week High trust Below market
Photonic IC Layout Cadence EDA) tools LVS DRC IC Layout PIC Electronic Design Automation
5+ yrs exp

Senior ASIC Engineer, Post Silicon Validation

Cisco

San Jose, CA 3 days ago $167,700–$245,200
Actively hiring Confirmed live yesterday Posted this week High trust Competitive pay
ASIC Post-Silicon Validation Python C I2C SPI JTAG PCIe Ethernet Firmware Bootloaders System Verilog UVM HBM DDR Oscilloscopes Traffic Generators DFT Scripting
7+ yrs exp

RF Silicon Software Engineer

SpaceX

Redmond, WA 3 days ago $125,000–$165,000
Actively hiring Confirmed live yesterday Posted this week High trust Below market
C C++ Python Embedded Software FPGA SystemVerilog Register Access PCB Layout Logic Analyzers Oscilloscopes Unit Testing Performance Optimization

Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Redmond, WA +3 3 days ago $165,000–$270,000
Actively hiring Confirmed live yesterday Posted this week High trust Above market
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up

Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Austin, TX +3 3 days ago
Actively hiring Confirmed live yesterday Posted this week Trusted
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization

FPGA/ASIC Design Engineer

SpaceX

Redmond, WA +1 3 days ago $125,000–$165,000
Actively hiring Confirmed live yesterday Posted this week High trust Below market
ASIC FPGA Verilog SystemVerilog VHDL RTL Design Python C C++ Bash DSP AXI AHB APB Vivado Quartus II VCS Questa Spyglass

Silicon Design Verification Engineer

Microsoft

3 days ago $102,100–$202,200
Actively hiring Confirmed live yesterday Posted this week High trust Below market
C C++ Python SystemVerilog FPGA Xilinx HAPS JTAG Logic Analyzers Oscilloscopes SoC Firmware Assembly AMBA AXI AHB APB SPI I2C I3C USB
2+ yrs exp Hybrid

Principal Silicon Engineer

Microsoft

3 days ago $142,800–$274,800
Actively hiring Confirmed live yesterday Posted this week High trust Competitive pay
RTL Design Static Timing Analysis Synthesis Physical Design Tcl Python PrimeTime Genus Innovus ICC2 UPF CDC RDC VCLP LINT PPA mixed‑signal Gate-level Power Analysis
8+ yrs exp Hybrid

Post-Silicon Memory Subsystem Validation Engineer

Amd

Austin, TX +1 3 days ago $133,200–$199,800
Actively hiring Confirmed live yesterday Posted this week High trust Below market
DDR LPDDR5x DDR5 Post-Silicon Validation First-Silicon Bring-up Root-Cause Analysis Firmware Memory Subsystems Pre-silicon Validation AI Automation

Senior Silicon Design Verification Engineer

Amd

Austin, TX 9 days ago $144,800–$217,200
Actively hiring Confirmed live yesterday High trust Competitive pay
UVM SystemVerilog Verilog C++ C SystemC TLM RTL Linux Windows Perl Ruby Shell Scripting Makefiles HLS ASIC Verification Simulation Firmware Graphics Pipeline
Hybrid

Senior Silicon Product Engineer, DFP - Manufacturing

Nvidia

Santa Clara, CA 10 days ago $168,000–$264,500
Actively hiring Confirmed live yesterday High trust Competitive pay
Silicon Validation high‑volume manufacturing Python MATLAB R SQL Data Analysis Test Methodology SoC GPU CPU Yield Analysis Scripting LLMs Copilots Anomaly Detection Pattern Recognition
6+ yrs exp Hybrid

Senior Silicon Product Definition Engineer

Nvidia

Santa Clara, CA 10 days ago $168,000–$264,500
Actively hiring Confirmed live yesterday High trust Above market
Python Perl SQL JMP BIOS Firmware Drivers Circuit Analysis Computer Architecture data-analysis Silicon Characterization Digital Design
8+ yrs exp Hybrid

Principal Chip Lead

Nvidia

Santa Clara, CA 10 days ago $232,000–$368,000
Actively hiring Confirmed live yesterday High trust Above market
SoC ASIC HBM SerDes High-speed I/O Power and Thermal Packaging Post-silicon Bring-up Silicon Validation System Integration Co-design AI Tools
10+ yrs exp Hybrid

Silicon Validation Engineer

Nvidia

Santa Clara, CA 11 days ago
Actively hiring Confirmed live yesterday High trust
ASIC Validation Silicon Bring-up System-level Debug PCIe STA Signal Integrity Firmware AI/ML LLM Telemetry HPC Observability
2+ yrs exp Hybrid

Principal RFIC Engineer

SpaceX

Irvine, CA +1 12 days ago $210,000–$340,000
Actively hiring Confirmed live yesterday Trusted Above market
RFIC Mixed-Signal SiGe GaAs GaN CMOS Spectre ADS HFSS Momentum IC floor planning Layout QPSK APSK QAM Spectrum Analyzers Vector Signal Analyzers Network Analyzers
8+ yrs exp