Principal Chip Lead

Nvidia

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$232,000–$368,000 / yr
Posted
17 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $215k
This role $300k
$144k most similar roles pay here $392k

This role pays more than 97% of similar roles. Most pay $180,629–$250,000 — the shaded band above. At the midpoint, this role pays about $300k versus about $215k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Principal Chip Lead

Principal Chip Lead, Silicon Co-Design Group serves as the technical lead for high-consequence silicon programs within the Silicon Co-Design Group. This role is not project management or a senior IC position; instead, it functions as the primary technical point of contact to resolve complex multi-functional bugs and provide a single technical perspective for leadership decisions. You will manage feature integration from chip to system, steward the qualification playbook, and lead Critical Debug and Technical Execution forums. The role requires expertise in SoC and ASIC architecture, specifically regarding subsystems like HBM, SerDes, power, thermal, high-speed I/O, or packaging. Candidates must possess over a decade of experience in post-silicon bring-up, validation, or system integration. You will translate ambiguous technical symptoms into root-cause closures while ensuring the technical integrity of products across Datacenter, Gaming, Robotics, Automotive, and Embedded markets.

What you'll do

  • Serve as the primary technical point of contact for multi-functional decisions and trade-offs.
  • Co-lead program-level feature integration from chip to system while resolving inter-function dependencies.
  • Resolve complex, multi-functional bugs in areas like HBM, power, thermal, and high-speed I/O.
  • Steward the qualification playbook and develop reusable methodologies for other programs.
  • Translate technical risks and trade-offs into decision-ready options for executive leadership.
  • Mentor other Chip Leads and contribute to organization-wide methodology through post-mortems.
  • Lead Critical Debug and Technical Execution forums to represent the chip's technical status.

What we're looking for

  • Hold a BS or MS in Electrical Engineering, Computer Engineering, or equivalent experience.
  • Possess over 15 years of experience in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company.
  • Demonstrate a proven track record of working on multiple shipped silicon products.
  • Possess a strong end-to-end understanding of SoC and ASIC architecture.
  • Exhibit recognized expertise in at least one subsystem such as HBM, SerDes, power and thermal, or packaging.
  • Provide specific examples of silicon-level impact including faster bring-up, fewer escapes, yield recovery, or methodology contributions.
  • Demonstrate the ability to guide technical decisions across functional boundaries without direct reporting authority.
  • Translate sophisticated silicon issues into clear, decision-ready options for executive audiences.

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