Principal Silicon Engineer

Microsoft

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$142,800–$274,800 / yr
Posted
2 days ago
Freshness
Confirmed live yesterday
Closes
Mar 28, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $220k
This role $209k
$127k most similar roles pay here $291k

This role pays less than 51% of similar roles. Most pay $193,472–$245,637 — the shaded band above. At the midpoint, this role pays about $209k versus about $220k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 518 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 505 roles with salary data.

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At a glance

TL;DR · Principal Silicon Engineer

As a Principal Silicon Engineer within the Interface IP Team, you will join the Silicon, Cloud Hardware, and Infrastructure Engineering group to develop core infrastructure for cloud hardware. You will own and drive microarchitecture and RTL design for complex silicon blocks and subsystems, translating system requirements into high-quality hardware implementations. Your daily work involves leading the capture and validation of design intent for digital and mixed-signal blocks while providing static timing leadership for mixed-signal interfaces across various corners. You will collaborate with RTL, physical design, and DFT teams to resolve cross-domain issues regarding timing, power, and functional requirements. The role requires expertise in RTL design, synthesis, PPA trade-offs, and tools like PrimeTime, Genus, and Innovus. Proficiency in Tcl and Python is required to improve design automation and execution efficiency for cloud infrastructure.

What you'll do

  • Drive microarchitecture and RTL design for complex silicon blocks and subsystems based on system requirements.
  • Capture and validate design intent for digital and mixed-signal blocks across front-end and physical flows.
  • Provide static timing leadership for mixed-signal interfaces to ensure closure and correlation across MMMC corners.
  • Resolve cross-domain issues regarding timing, power, and functional requirements with RTL, PD, and DFT teams.
  • Develop design automation using AI and constraint-checking to improve execution efficiency and PPA.
  • Communicate data-driven status, risks, and mitigation plans to program leadership.

What we're looking for

  • A Doctorate plus 3 years experience, Master's plus 6 years, or Bachelor's plus 8 years of technical engineering experience is required.
  • Candidates must be able to pass a Microsoft Cloud Background Check and meet export control regulations.
  • Proof of citizenship, residency, or other protected status is required for access to export-controlled information.
  • Experience leading projects from beginning-to-end is preferred.
  • 8+ years of experience in RTL design and design checks (CDC/RDC/VCLP/LINT) is preferred.
  • 8+ years of experience in Synthesis, Timing constraints, and Power Performance Area (PPA) trade-offs is preferred.
  • Proficiency in RTL to Physical Design collateral development, Tcl, Python, and static timing analysis is preferred.
  • Experience with industry tools for synthesis, STA, and PD flows, as well as knowledge of full RTL2GDS flow, is preferred.

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