Senior Silicon Power, Thermal Validation and Methodology Engineer

Nvidia

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Employment
Full-time
Posted
34 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k
This role $216k
$149k $277k
below market most similar roles pay here above market

This role pays more than 66% of similar roles. Most pay $177,250–$233,400 — the blue band above. At the midpoint, this role pays about $216k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Silicon Power, Thermal Validation and Methodology Engineer

The Senior Silicon Power, Thermal Validation and Methodology Engineer joins the Silicon Design for Productization team within the Silicon Co-Design Group. This role involves leading multi-functional efforts to maintain power and thermal productization strategies, creating silicon test plans, and developing characterization processes, debug tools, and fuse settings. The engineer will drive root-cause closure for silicon issues, steward the power and thermal playbook, and build AI-enabled workflows to automate data analysis and metric extraction. Key requirements include a BS or MS in Electrical Engineering or Computer Engineering and over eight years of experience in post-silicon bring-up and validation for ASIC or SoC programs. The work addresses complex problems at the intersection of architecture, workload behavior, silicon variation, firmware policy, and platform constraints to ensure product performance and reliability.

What you'll do

  • Lead multi-functional teams to execute the program’s power and thermal productization strategy.
  • Create silicon test plans, characterization processes, debug tools, and firmware settings based on controller designs.
  • Resolve challenging silicon issues using structured hypotheses, measurement plans, and root-cause analysis.
  • Develop new power and thermal mitigations and reusable methodologies when existing processes are insufficient.
  • Build AI-enabled workflows to automate data analysis, metric extraction, and report generation for multiple bring-ups.
  • Serve as a technical owner for multi-functional decisions and tradeoffs regarding feature bring-up.

What we're looking for

  • BS or MS in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
  • 8+ years of proven track record in post-silicon bring-up and validation of power and thermal features on sophisticated ASIC or SoC programs.
  • Strong end-to-end understanding of silicon behavior across architecture, firmware, validation, and platform interactions with expertise in power and thermal domains.
  • Evidence of creating or improving characterization docs, debug tools, dashboards, or other reviewable technical artifacts.
  • Demonstrated ability to make sound tradeoff decisions across power, thermal, performance, firmware, design, validation, and schedule constraints.
  • Experience building or applying AI-enabled workflows for silicon characterization or validation with measurable workflow impact and clear guardrails.
  • A history of building technical power and thermal methodology, such as debug frameworks, validation standards, or characterization infrastructure (preferred).
  • Experience with silicon power measurement, energy-efficiency tuning, or analytics that improved bring-up, signoff, or validation workflows (preferred).

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