This role pays more than
73%
of similar roles. Most pay
$177,087–$220,125
— the shaded band above.
At the midpoint, this role pays about
$216k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
1150 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 912 roles with salary data.
The Senior Memory Post Silicon Qualification Engineer joins the Silicon Co-Design Group to manage high-speed memory bring-up, characterization, and qualification for flagship GPU, CPU, and SoC programs. This role focuses on root-causing complex memory marginality issues across DRAM, controllers, PHYs, and boards before software hardening. The engineer will perform functional validation, IO tuning, and timing margin analysis while developing AI-accelerated workflows to automate shmoo bucketing and failure signature detection. Key responsibilities include designing post-Si validation plans and collaborating with global teams to resolve multi-team failures involving silicon, firmware, and manufacturing. Required expertise includes deep knowledge of GDDR, LPDDR, or HBM protocols, along with proficiency in using oscilloscopes, DMMs, and protocol analyzers. The role addresses critical memory performance challenges where architecture, packaging, and manufacturing intersect to ensure reliable high-performance computing systems.
Develop productized fixes and reusable playbooks to resolve ambiguous memory marginality before software hardening.
Design and deploy AI-enabled workflows for automated shmoo bucketing and failure signature detection.
Translate new memory features into targeted post-Si validation plans in collaboration with pre-Si teams.
Analyze large datasets of margin and characterization data to provide decision-ready insights for qualification.
What we're looking for
B.Tech or M.Tech in Electrical, Electronics, or Computer Engineering (or equivalent experience).
10+ years of semiconductor industry experience.
At least 3 years of experience in memory interface bring-up, characterization, and qualification on shipped silicon.
Deep protocol and physical-layer understanding of GDDR, LPDDR, or HBM including training, calibration, and IO tuning.
Strong hands-on lab fundamentals with oscilloscopes, DMMs, thermal chambers, and protocol analyzers.
Working knowledge of PCB stack-up, board layout, power planes, and SI/PI guidelines.
Demonstrated experience building AI-driven workflows for memory characterization, margin analysis, or failure triage.
Experience resolving ambiguous failures to root-cause closure with codified fixes (preferred); history of building reusable qualification methodologies (preferred).
DDR
LPDDR
C
C++
Python
Arm Assembly
Linux
Bare-Metal
Post-Silicon Validation
Characterization
PHY
Firmware
Logic Analyzers
SoCs
Data Analysis
Automation
Scripting