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PCIe CXL AXI CHI Verilog SystemVerilog RTL design performance analysis power optimization Docker CI/CD Linux +7 more Show less

RTL Verilog SystemVerilog VHDL ASIC LPDDR HBM NoC CPU x86 ARM Cache Controller Memory Subsystem Digital Design Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis RTL Design Verification +15 more Show less

C++ SystemC HBM Memory_Hierarchies DRAM_Systems AI/ML GPU HPC Post_Silicon_Performance_Analysis SoC_Architecture TLM HBM2 HBM2E HBM3 +9 more Show less

CADENCE SPICE MATLAB Verilog VHDL Python C++ Perl Tcl Git SVN JIRA Confluence Ansys RHEL Linux Windows PowerShell Spectre HSpice Calibre QuestaSim ModelSim SonarQube CI/CD +20 more Show less

PCIe CXL AXI CHI Verilog SystemVerilog RTL design performance analysis power optimization Docker CI/CD Linux +7 more Show less

Verilog SystemVerilog UVM SerDes CDR DFE CTLE TXFIR Python Perl Tcl VHDL ModelSim Cadence Calibre Linux Git SVN PCIe Ethernet InfiniBand USB C++ MATLAB +19 more Show less

Altium Cadence Allegro AutoCAD Electrical HyperLynx SIwave PIvision Python MATLAB HFSS ANSYS Sigrity Xilinx Vivado FPGA PCIe DDR SerDes EMI/EMC standards Differential pairs Controlled impedance routing Length matching Stackup design +16 more Show less

PCB CAN I2C SPI Ethernet RS232 RS422 RS485 USB PowerDesign Microcontrollers MixedSignalPCBs ThermalTesting EMITesting SoftwareDebuggingTools FirmwareDevelopment HighSpeedAirVehicles DefenseSystems TemperatureEffects VibrationEffects +15 more Show less

Verilog SystemVerilog UVM RTL PCIe Ethernet Static Timing Analysis Formal Verification Tools Custom Digital Circuit Design High-Speed SerDes I/O FFE DFE CTLE CDR Offset Cancellation +10 more Show less