Principal Design Engineer - High-Speed Interconnect

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$249,900–$338,100 / yr
Posted
72 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $210k
This role $294k
$128k most similar roles pay here $361k

This role pays more than 97% of similar roles. Most pay $177,250–$242,212 — the shaded band above. At the midpoint, this role pays about $294k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

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At a glance

TL;DR · Principal Design Engineer - High-Speed Interconnect

As a Principal Design Engineer – High-Speed Interconnect, you will join the team to own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems including PCIe, CXL, and UALink across multiple silicon products. You will translate system requirements into implementation-ready specifications, manage the development process from concept through synthesis preparation, and collaborate with cross-functional teams to meet performance, power, and area targets. The role requires deep expertise in SystemVerilog and high-performance digital subsystems, alongside a strong understanding of AXI, CHI, ACE, APB, and streaming interfaces. You will solve complex problems regarding transaction flows, memory expansion, and coherent connectivity while analyzing traffic patterns and buffer requirements. Key technical domains include CDC, RDC, and low-power builds, ensuring robust performance for high-speed I/O subsystems and sophisticated interconnect architectures in a semiconductor environment.

What you'll do

  • Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems like PCIe, CXL, and UALink.
  • Translate system and protocol requirements into implementation-ready specifications, register definitions, and synthesizable RTL.
  • Manage the full development lifecycle from initial concept through RTL creation, verification support, and final delivery.
  • Analyze traffic patterns, workloads, and buffer requirements to guide technical implementation tradeoffs.
  • Lead technical reviews and debug cross-functional issues across architecture, firmware, and physical design teams.
  • Improve building methodologies and mentor engineers to ensure high performance and reliability.
  • Ensure all designs meet specific functionality, bandwidth, latency, power, area, and timing targets.

What we're looking for

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 8+ years of experience in RTL build, microarchitecture, subsystem integration, or related semiconductor roles.
  • Deep hands-on expertise in SystemVerilog and the development of high-performance digital subsystems.
  • Deep understanding of PCIe, CXL, and UALink transaction flows, ordering, flow control, and error handling.
  • Experience with coherent/non-coherent interconnects, cache hierarchies, memory systems, and high-speed I/O subsystems.
  • Strong understanding of AXI, CHI, ACE, APB, streaming interfaces, buffering, arbitration, scheduling, and backpressure.
  • Experience with CDC, RDC, reset sequencing, low-power build, lint, formal verification, synthesis, timing analysis, and waveform debug.
  • Experience with PCIe Gen6+, CXL 2.0+, chiplets, or die-to-die connectivity (preferred).

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