High Speed Analog I/O Designer

Broadcom

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $143,800–$230,000 / yr
Employment: Full-time
Posted: 79 days ago
Freshness: Confirmed live today
Closes: Jan 20, 2027
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $216k

This role $187k

$129k $279k

below market most similar roles pay here above market

This role pays less than 64% of similar roles. Most pay $177,250–$254,750 — the blue band above. At the midpoint, this role pays about $187k versus about $216k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 241 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 161 roles with salary data.

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At a glance

TL;DR · High Speed Analog I/O Designer

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As a High Speed Analog I/O designer, you will join the hardware engineering team to design and optimize cutting-edge interface buffer chips for DDR, LP5, 5X, 6, and chiplets using the latest FinFET process nodes. Your daily responsibilities include identifying circuit architectures, designing and simulating high-speed DDR circuits, and enhancing transmitter and receiver circuits such as CTLE, VGA, DFE, and slicers. You will focus on performance metrics like sensitivity, linearity, and power consumption while overseeing physical layout to minimize parasitics. Required expertise includes high-speed RX and Analog-Front-End design, FIR filters, slew rate control, and voltage or current mode drivers. You must be proficient with Cadence Virtuoso, Maestro, Spectre, and HSPICE to solve complex signal integrity and reliability challenges.

Skills

Analog Design DDR FinFET CTLE DFE Cadence Virtuoso Maestro Spectre HSPICE Signal Integrity Serializer De-serializer Chiplet RX Design Power Management Timing Analysis

What you'll do

Design, simulate, and optimize high-speed DDR circuits and chiplet I/Os.
Design and enhance transmitter and receiver circuits including CTLE, VGA, DFE, and slicers.
Develop circuit architectures to improve power, area, and performance targets.
Oversee physical layout to minimize the effects of parasitics and process variation.
Conduct thorough simulations to validate design performance and reliability.
Troubleshoot design issues and implement necessary corrective actions.
Analyze customer silicon data to identify and implement design enhancements.
Create clear and detailed design reports for technical stakeholders.

What we're looking for

Master's or Ph.D. in Electrical Engineering, Electronics Engineering, or a related field.
At least 10 years of experience in analog design, focusing on high-speed RX and Analog-Front-End design.
Experience with FinFET technologies.
Expertise in high-speed DDR I/O interface, chip-chip interface design, and optimization.
Strong knowledge of analog receiver circuits such as CTLE, DFE, and FEE.
Sound knowledge of transmitter circuits such as FIR filter, slew rate control, voltage, and current mode drivers.
Knowledge of design for reliability (EM, IR, aging, self-heating) and layout effects.
Proficiency with analog design tools such as Cadence Virtuoso, Maestro, Spectre, and HSPICE.

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