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SystemVerilog Verilog RTL Xilinx Vivado Intel Quartus Questa Xcelium VCS AMBA PCIe CXL.cache AXI AXIS FPGA high-performance digital design memory coherency data structures simulation tools logic analyzers protocol analyzers +15 more Show less

Vivado Verilog VHDL Xilinx SoC ARM ModelSim Quartus C Python +5 more Show less

VHDL Verilog Altium Designer DO-254 DO-178C DO-160 DO-311A MIL-STD-810 MIL-STD-704 MIL-STD-461 +5 more Show less

SystemVerilog UVM SVA Questa VCS Xcelium Git Linux Python Tcl Makefile SVUnit Formal verification CDC verification CI/CD Nix DO-254 +12 more Show less

Vivado Xilinx Versal VHDL Verilog C C++ ARM Ethernet Serial Analog Digital ModelSim Quartus CI/CD +10 more Show less

Vivado Verilog VHDL Xilinx SoC ModelSim Quartus C C++ FPGA SoC ARM-based systems Safety-critical design High speed busses +8 more Show less

VHDL Verilog SystemVerilog Xilinx Linux Git gcc PCIe JESD Python C++ Secret security clearance Embedded Linux Wireless comms Radar systems RF test equipment Xilinx AI Engines NVIDIA CUDA +13 more Show less

SystemVerilog VHDL Xilinx Vivado FPGA Digital Signal Processing Radar Systems Timing Analysis Resource Optimization Design Verification DO-254 Git PCIe JESD204B RFSoC Zynq UltraScale+ High-Speed Interfaces Embedded Software Development MATLAB +14 more Show less

VHDL Verilog Altium Designer DO-254 DO-178C MIL-STD-810 MIL-STD-704 MIL-STD-461 +3 more Show less

Vivado Xilinx Verilog VHDL ModelSim Quartus C Python Git JIRA Confluence CI/CD PostgreSQL AWS Kubernetes +10 more Show less

Verilog SystemVerilog VHDL FPGA SoC Xilinx RFSoC AD9361 DSP C C++ FFT FIR filter IIR filter RTL Python +11 more Show less

Verilog SystemVerilog VHDL Xilinx SoC FPGA C C++ Python Perl Bash DSP algorithms GbE PCI-E Ethernet 802.3 IPV4/IPV4 UDP TCP +11 more Show less

SystemVerilog Verilog Python C C++ Bash DSP AXI AHB APB FPGA ASIC Microprocessors Oscilloscopes Spectrum Analyzers +10 more Show less

FPGA Vivado Protocompiler HAPS ChipScope Synthesis Place_and_Route Timing_Closure Oscilloscopes Logic_Analyzers Protocol_Analyzers CI/CD Git Python Jenkins PostgreSQL Kubernetes AWS +13 more Show less

Vivado Xilinx FPGA RTL Python Perl MATLAB Fixed_point_design Multiple_clock_domain_FPGA_designs Digital_signal_processing Wireless_communication_systems +6 more Show less

Vivado Lattice Radiant System Verilog Verilog I2C SPI UART USB MIPI DP Python Tcl CI/CD Git CDC FPGA C C++ High-speed serial interfaces +14 more Show less

Vivado Lattice Radiant System Verilog Verilog I2C SPI UART USB MIPI DP Python Tcl CI/CD Git CDC FPGA C C++ High-speed serial interfaces +14 more Show less

FPGA Xilinx Altera Microchip Lattice UVM ASIC DFT Signal_Integrity Python PostgreSQL CI/CD AWS Kubernetes Git Schematics Layout Troubleshooting High_Speed_Board_Design Ethernet Wireless_Protocol PoE_PSE_PD Gigabit_Ethernet Multigigabit_Ethernet 10_Gigabit_Ethernet 25G_Ethernet 100G_Ethernet 400G_Ethernet 800G_Ethernet +24 more Show less

Verilog System Verilog Xilinx AMD Microchip Microsemi SPI I2C UART SpaceWire Gigabit Ethernet PCIe 802.11 Python Tcl Bash Linux C C++ UVM Formal methods +16 more Show less

SystemVerilog RTL/HDL FPGA Xilinx Intel C++ Python Linux ARM AXI PCIe I2C LVDS Ethernet Git JIRA Agile +12 more Show less