Space Systems Engineering Integration & Test Engineer, TIDES FPGA

General Dynamics

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Scottsdale, AZ
Salary: $114,441–$126,958 / yr
Posted: 13 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $164k

This role $121k

$105k $204k

below market most similar roles pay here above market

This role pays less than 89% of similar roles. Most pay $135,000–$192,000 — the blue band above. At the midpoint, this role pays about $121k versus about $164k for comparable roles.

Based on 240 similar postings.

Employer

About General Dynamics

General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.

General Dynamics currently has 1379 open roles on FindRole.

Listed pay typically runs $124,093–$150,385 across 1186 roles with salary data.

Most-posted roles

View all roles at General Dynamics

At a glance

TL;DR · Space Systems Engineering Integration & Test Engineer, TIDES FPGA

Role Posting Log in to save

As a Space Systems Engineering Integration & Test Engineer - TIDES FPGA (PIE), you will join the Payload Integration and Evolution team to develop and evolve the Payload Verification Platform. This hardware development environment utilizes COTS and custom FPGA boards to emulate spacecraft payload behavior for early integration and risk reduction. You will architect and lead FPGA-enabled capabilities, managing everything from requirements and microarchitecture to RTL implementation, simulation, timing closure, and lab bring-up. Key responsibilities include driving real-time functions like packet timestamping and precision command scheduling. You will utilize SystemVerilog, VHDL, and vendor toolchains like Vivado or Lattice Diamond. Required skills include experience with Ethernet, SPI, and UART interfaces, along with proficiency in Python, Tcl, and Linux for automation and CI/CD workflows.

Skills

FPGA RTL SystemVerilog VHDL Vivado Lattice Diamond Python Tcl Linux CI/CD Git Ethernet SPI UART JESD204B/C Oscilloscope Logic Analyzer JTAG Digital Design Timing Closure

What you'll do

Architect, design, and integrate COTS and custom FPGA-based platforms to emulate spacecraft payload behavior.
Lead RTL development, simulation, interface integration, timing closure, and lab bring-up for FPGA-enabled test capabilities.
Define hardware integration approaches that bridge test equipment, payload hardware, and software infrastructure.
Drive real-time test functions including payload interface emulation, packet timestamping, and precision command scheduling.
Lead structured debug efforts using lab instrumentation, waveform analysis, and root-cause investigation.
Document architecture, interface definitions, bring-up procedures, and release artifacts.
Mentor junior engineers and contribute to design reviews, technical roadmaps, and platform evolution.

What we're looking for

U.S. citizenship is required.
Must be able to obtain a TS/SCI security clearance within a reasonable amount of time.
Bachelor's degree in Electrical or Computer Engineering, or a related field, plus 2 years of relevant experience.
Master's degree plus 6 months of relevant experience.
Significant experience with FPGA design, RTL development, hardware integration, and lab bring-up (preferred).
Proficiency with SystemVerilog and/or VHDL, simulation, timing constraints, and FPGA vendor toolchains (preferred).
Experience integrating FPGA interfaces such as Ethernet, SPI, UART, or high-speed serial links (preferred).
Proficiency with scripting and automation using Python, Tcl, or Linux shell (preferred).