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Active Keyword: FPGA Design Eng Remove filter Clear all

20 of up to 20 (filtered)

Senior Hardware Design Engineer, LEO KMM FPGA

Amazon Inc

San Diego, CA +2 2 days ago $137,300–$185,700
Actively hiring Posted this week Verified listing Below market
RF PCB Schematic Capture DVT Qualification Production Test ASIC Subsystem Design Prototyping Signal Characterization Manufacturing Engineering RF Avionics Troubleshooting Debugging Firmware Integration Factory Software
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ASIC & FPGA Design Engineer Sr

Lockheed Martin

Orlando, FL 3 days ago
Actively hiring Posted this week Verified listing
VHDL Verilog SystemVerilog Xilinx Vivado AMD Vitis Synopsys VCS AXI Ethernet TCP/IP PCIe GitLab UVM Simulink C C++ MATLAB Python Synplify ChipScope
Hybrid
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FPGA Design Engineer Lead

Lockheed Martin

Orlando, FL 3 days ago
Actively hiring Posted this week Verified listing
VHDL Verilog SystemVerilog UVM GitLab Xilinx Vivado AMD Vivado Synopsys VCS Git C C++ MATLAB Simulink Synplify NCSim ChipScope Simulink HDL Coder CI/CD
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FPGA Design Engineer

Lockheed Martin

Boulder, CO 3 days ago $82,900–$146,165
Actively hiring Posted this week Verified listing Below market
Vivado Verilog VHDL Xilinx Vitis High-Level Synthesis (HLS) C++ Matlab FPGA Vitis Model Composer Matlab HDL Coder embedded software development embedded Linux Yocto
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Senior Firmware FPGA Design Engineer

Lockheed Martin

Owego, NY 3 days ago $101,000–$178,135
Actively hiring Posted this week Verified listing Below market
FPGA Verilog System Verilog VHDL MATLAB Python C/C++ TCL Jira Confluence UVM Mentor Questa HDL Simulator Intel Quartus Xilinx Vivado Microchip Libero
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ASIC & FPGA Design Engineer Senior

Lockheed Martin

Orlando, FL 3 days ago
Actively hiring Posted this week Verified listing
VHDL Verilog SystemVerilog Xilinx Vivado AMD Vitis UltraScale design methodology Synopsys VCS AXI Ethernet TCP/IP PCIe Serial protocols High-speed oscilloscopes Spectrum analyzers Signal generators Synopsys EDA tools Simulink HDL Coder C/C++ DSP
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Senior Firmware FPGA Design Engineer

Lockheed Martin

Liverpool, NY 3 days ago $101,000–$178,135
Actively hiring Posted this week Verified listing Below market
FPGA Verilog VHDL Xilinx Vivado Intel Quartus Mentor Questa HDL UVM MATLAB Python C/C++ DSP CUDA OpenCL Simulink HDL Coder Vivado HLS
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Staff FPGA Design Engineer

Lockheed Martin

Owego, NY 3 days ago $123,500–$217,695
Actively hiring Posted this week Verified listing Below market
FPGA Verilog VHDL SystemVerilog MATLAB Python C C++ Intel Quartus Xilinx Vivado Microchip Libero Mentor Questa HDL UVM Agile Jira Confluence
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ASIC & FPGA Design Engineer, Senior

Lockheed Martin

Orlando, FL 3 days ago
Actively hiring Posted this week Verified listing
VHDL Verilog Xilinx Intel Vivado Quartus MATLAB Simulink High-Level Synthesis Power Analysis Thermal Analysis Design Assurance Configuration Management Mentorship ASIC Design FPGA Co-Design Hardware-Software Co-Verification
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ASIC & FPGA Design Engineer Senior

Lockheed Martin

Liverpool, NY 3 days ago $101,000–$178,135
Actively hiring Posted this week Verified listing Below market
VHDL Xilinx Vivado Intel Quartus Mentor Questa HDL UVM FPGA DSP MATLAB CUDA OpenCL Simulink HDL Coder Xilinx System Generator Digital Signal Processing Radar Electronic Warfare
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ASIC/FPGA Design Engineer IV

Lockheed Martin

Littleton, CO 3 days ago $123,500–$217,695
Actively hiring Posted this week Verified listing Below market
VHDL Verilog SystemVerilog Linux FPGAs Digital ASICs Mixed-signal ASICs Atlassian JIRA Microsoft Project Earned Value Management System CI/CD
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ASIC FPGA Design Engineer V

Lockheed Martin

North Andover, MA 3 days ago $145,200–$255,990
Actively hiring Posted this week Verified listing Competitive pay
VHDL Verilog SystemVerilog Linux AMD_Xilinx_Vivado Microchip_Libero MS_Project JIRA Earned_Value_Management_System CI/CD
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Senior FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA 20 days ago $125,000–$195,000
Actively hiring Below market
Xilinx Vivado FPGA RTL MATLAB Fixed_point_arithmetic Digital_signal_processing Multiple_clock_domain_designs High_utilization_FPGA_designs
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FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX

Redmond, WA 24 days ago $125,000–$145,000
Actively hiring Verified listing Below market
SystemVerilog Verilog Python C C++ Bash DSP AXI AHB APB FPGA ASIC Microprocessors Oscilloscopes Spectrum Analyzers
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Principal FPGA / RTL Design Engineer - Signal Processing

Motorola Solutions

Los Angeles, CA 27 days ago $175,000–$225,000
Actively hiring Competitive pay
Vivado Xilinx FPGA RTL Python Perl MATLAB Fixed_point_design Multiple_clock_domain_FPGA_designs Digital_signal_processing Wireless_communication_systems
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FPGA Prototyping Design Engineer

Apple Inc

Sunnyvale, CA 60 days ago $126,800–$220,900
Actively hiring Competitive pay
Verilog SystemVerilog Xilinx FPGA Vivado IP Integrator Linux Python Tcl Git PCIe I2C SPI UART High-speed SERDES IEEE 802.11 Bluetooth Synopsys HAPS Make TeamCity
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Wireless FPGA Prototype Design Engineer

Apple Inc

San Francisco, CA 63 days ago $126,800–$220,900
Actively hiring Competitive pay
FPGA Verilog Python Perl Shell C JTAG Oscilloscope Logic Analyzer LitePoint Palladium IEEE 802.11 Bluetooth APB AHB AXI USB I2C SPI
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Senior FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA +1 80 days ago $125,000–$195,000
Actively hiring Below market
Vivado Xilinx FPGA RTL MATLAB Fixed_point_arithmetic Digital_signal_processing Multiple_clock_domain_designs High_utilization_FPGA_designs
Hybrid
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