Wireless FPGA Prototype Design Engineer

Apple Inc

Quick summary

Work type
On-site
Location
San Francisco, CA
Salary
$126,800–$220,900 / yr
Posted
41 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $181k
This role $174k
$116k most similar roles pay here $232k

This role pays less than 55% of similar roles. Most pay $155,275–$205,750 — the shaded band above. At the midpoint, this role pays about $174k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Wireless FPGA Prototype Design Engineer

Join Apple’s dynamic wireless silicon development team as a Wireless FPGA Prototype Design Engineer, where you will play a crucial role in developing signal processing-intensive designs for wireless communication SoCs. Your responsibilities include ASIC prototyping from requirements through implementation and lab debugging, FPGA synthesis with timing constraints definition and closure, maintaining common design platforms, and bringing up, debugging, and testing FPGA/emulation models. You will also support pre-silicon and post-silicon validation efforts. Ideal candidates have experience in FPGA flow, digital design, chip architecture, scripting languages like Shell, C, Python or Perl, and hands-on lab equipment expertise. Familiarity with AMD’s Verilog-based design entry, synthesis, place-and-route processes, and wireless standards such as IEEE 802.11 and Bluetooth is preferred.

What you'll do

  • Design and implement ASIC prototypes for wireless communication SoCs.
  • Perform FPGA synthesis and define timing constraints for efficient design.
  • Maintain a common design platform for both ASIC and FPGA projects.
  • Debug and test FPGA/emulation models in the lab environment thoroughly.
  • Support pre-Silicon and post-silicon validation processes effectively.

What we're looking for

  • Extensive experience in FPGA flow and synthesis.
  • Proficiency in digital design, chip architecture, and microarchitecture.
  • Hands-on lab equipment experience for bring-up and debug.
  • Scripting expertise with languages like Shell, C, Python or Perl.
  • Knowledge of wireless standards such as IEEE 802.11 and Bluetooth.
  • Familiarity with AMD’s flow including Verilog design entry and timing closure.
  • Strong problem-solving skills in FW/HW development environments.

More like this

Similar roles

Wireless FPGA Prototype Design Engineer

Apple Inc

San Francisco, CA 21 days ago $181,100$318,400
FPGA Verilog Python Perl Shell C JTAG Oscilloscope Logic Analyzer LitePoint Palladium IEEE 802.11 Bluetooth APB AHB AXI USB I2C SPI

Wireless SoC Design Engineer

Apple Inc

Sunnyvale, CA 38 days ago $126,800$220,900
SystemVerilog RTL Lint CDC RDC Synthesis STA Memory_subsystems Bus_interfaces CPU_integration DMA_engines Compression Security_IP_design PCIE QSPI UART SPMI Cross_clock_domain_design ASIC_low_power_design Multiple_supply_domains Dynamic_power_scaling Power_analysis DFT Scan_insertion Memory_BIST

Wireless SoC Design Engineer

Apple Inc

San Diego, CA 38 days ago $120,300$210,100
SystemVerilog RTL Lint CDC RDC Synthesis STA MemorySubsystemDesign BusInterfaces CPUIntegration DMAEngines CompressionIP SecurityIP PCIE QSPI UART SPMI CrossClockDomainDesign ASICLowPowerDesign DFT ScanInsertion MemoryBIST

Wireless Design Engineer

Apple Inc

Sunnyvale, CA 29 days ago $181,100$318,400
RTL SystemVerilog Verilog Python Perl Shell CDC RDC STA Lint ASIC MAC Bluetooth WLAN Zigbee AXI APB AHB Memory systems Power management Encryption/decryption engines High-speed data path Control units

Cellular ASIC Design Engineer

Apple Inc

Austin, TX 38 days ago
Python Perl TCL Unix shell C/C++ Hspice Finesim AFS Spectre Infinisim RedHawk SeaHawk Voltus ICC2 Fusion Innovus Aprisa PT PT-SI Tempus DC/DCT/DCG/Genus/Oasis Design Technology Co-optimization ML modeling

Cellular ASIC Design Engineer

Apple Inc

Sunnyvale, CA 38 days ago $212,000$386,300
Python Perl TCL Unix_shell C C++ Hspice Finesim AFS Spectre Infinisim RedHawk SeaHawk Voltus ICC2 Fusion Innovus Aprisa PT PT-SI Tempus DC/DCT/DCG/Genus/Oasis Design_for_Test DFT ATPG Machine_Learning EDA_tools VLSI RTL_to_GDSII_flows