Principal FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Los Angeles, CAIrvine, CA
Salary
$175,000–$225,000 / yr
Posted
102 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $194k
This role $200k
$151k most similar roles pay here $233k

This role pays more than 55% of similar roles. Most pay $171,500–$216,250 — the shaded band above. At the midpoint, this role pays about $200k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Motorola Solutions

Motorola Solutions, Inc. (NYSE: MSI) is a leading American technology company providing mission-critical communications, video security, and analytics for public safety and enterprise customers.

Motorola Solutions currently has 135 open roles on FindRole.

Listed pay typically runs $106,500–$140,000 across 117 roles with salary data.

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At a glance

TL;DR · Principal FPGA / RTL Design Engineer, Signal Processing

Role Posting Log in to save

The Principal FPGA / RTL Design Engineer joins the FPGA Engineering team to support the research and development of advanced wireless systems. This role involves the entire lifecycle from concept to field deployment, focusing on the efficient implementation of novel signal processing algorithms for MIMO wireless networking products. Key responsibilities include digital design architecting, fixed point design of signal processing blocks, RTL coding, simulation, test bench development, FPGA synthesis, and timing closure. The candidate will also perform hardware verification, troubleshooting with logic analyzers, and provide support to RF and Software Engineering teams. Required technical skills include experience with Xilinx FPGAs, SoCs, the Vivado IDE, and fixed point binary arithmetic. Preferred competencies include MATLAB, Python, and Perl scripting. The work addresses complex real-world communication needs for mission-critical applications in challenging environments.

Skills

FPGA RTL Design Xilinx Vivado Digital Signal Processing Python Perl MATLAB Logic Analyzers Timing Closure Simulation test bench development Wireless Communication Systems

What you'll do

  • Architect digital designs for wireless communication projects.
  • Implement fixed-point signal processing blocks in collaboration with systems engineers.
  • Perform RTL coding, simulation, and test bench development.
  • Execute FPGA synthesis and achieve timing closure.
  • Conduct hardware verification and troubleshooting using logic analyzers.
  • Provide technical support to the RF and Software Engineering teams.
  • Develop and implement novel signal processing algorithms for MIMO wireless networking products.

What we're looking for

  • Must be a U.S. Person (U.S. Citizen or Permanent Resident).
  • Bachelor of Science degree in Electrical Engineering, Computer Science, or a related field.
  • Minimum 10 years of experience in RTL design and FPGA implementation with a Bachelor's degree.
  • Minimum 8 years of experience in RTL design and FPGA implementation with a Master's degree.
  • Minimum 6 years of experience in RTL design and FPGA implementation with a PhD.
  • Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
  • Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.

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