Principal FPGA / RTL Design Engineer - Signal Processing

Motorola Solutions

Hybrid

Quick summary

Work type
Hybrid
Location
Los Angeles, CA
Salary
$175,000–$225,000 / yr
Posted
3 days ago
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $185k
This role $200k
$141k most similar roles pay here $234k

This role pays more than 60% of similar roles. Most pay $153,100–$216,250 — the shaded band above. At the midpoint, this role pays about $200k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Motorola Solutions

Motorola Solutions, Inc. (NYSE: MSI) is a leading American technology company providing mission-critical communications, video security, and analytics for public safety and enterprise customers.

Motorola Solutions currently has 103 open roles on FindRole.

Listed pay typically runs $110,250–$145,000 across 90 roles with salary data.

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At a glance

TL;DR · Principal FPGA / RTL Design Engineer - Signal Processing

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Silvus is hiring a Principal FPGA/RTL Design Engineer to join the FPGA Engineering team, reporting directly to the Director of FPGA Engineering. This senior role involves architecting digital designs for wireless communication projects, including fixed-point design of signal processing blocks, RTL coding and simulation, FPGA synthesis, and hardware verification. The ideal candidate will have extensive experience with Xilinx FPGAs and SoCs using Vivado IDE, as well as proficiency in scripting languages like Perl and Python. They must possess strong skills in digital signal processing and multiple clock-domain FPGA designs to support complex wireless systems R&D aimed at solving real-world communication challenges.

Skills

Vivado Xilinx FPGA RTL Python Perl MATLAB Fixed_point_design Multiple_clock_domain_FPGA_designs Digital_signal_processing Wireless_communication_systems

What you'll do

  • Design digital architectures for wireless communication projects.
  • Implement fixed-point signal processing blocks in collaboration with systems engineers.
  • Develop RTL code, simulations, and test benches for FPGA-based designs.
  • Achieve FPGA synthesis and timing closure for high-utilization designs.
  • Troubleshoot hardware issues using logic analyzers and verification tools.

What we're looking for

  • Minimum 6 to 10 years of experience in RTL design and FPGA implementation.
  • Bachelor’s degree or higher in Electrical Engineering, Computer Science, or related field.
  • Expertise in fixed point binary arithmetic and digital signal processing designs.
  • Proven ability to work with multiple clock-domain, high-utilization FPGA designs.
  • Experience using Xilinx FPGAs, SoCs, and the Vivado IDE.
  • Strong communication skills and proficiency in scripting languages like Perl and Python.

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