Senior FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Confirmed live yesterday Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
Los Angeles, CAIrvine, CA
Salary
$125,000–$195,000 / yr
Posted
95 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k
This role $160k
$114k most similar roles pay here $230k

This role pays less than 82% of similar roles. Most pay $170,000–$215,075 — the shaded band above. At the midpoint, this role pays about $160k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Motorola Solutions

Motorola Solutions, Inc. (NYSE: MSI) is a leading American technology company providing mission-critical communications, video security, and analytics for public safety and enterprise customers.

Motorola Solutions currently has 135 open roles on FindRole.

Listed pay typically runs $106,500–$140,000 across 117 roles with salary data.

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At a glance

TL;DR · Senior FPGA / RTL Design Engineer, Signal Processing

Role Posting Log in to save

Senior FPGA / RTL Design Engineer - Signal Processing joins the FPGA Engineering team to support the research and development of advanced wireless systems. This role involves participating in the entire lifecycle from concept to field deployment, specifically focusing on the efficient implementation of novel signal processing algorithms for MIMO wireless networking products. Key responsibilities include digital design architecting for wireless communication projects, fixed point design of signal processing blocks, RTL coding, simulation, test bench development, and FPGA synthesis with timing closure. The candidate will utilize Xilinx FPGAs, SoCs, and the Vivado IDE while performing hardware verification and troubleshooting using logic analyzers. Essential skills include expertise in multiple clock-domain, high-utilization designs and fixed point binary arithmetic. This role addresses complex real-world communication needs within the domain of advanced MANET and MIMO communications systems.

Skills

FPGA Digital Signal Processing RTL Xilinx Vivado MATLAB Logic Analyzers Hardware Verification Timing Closure Synthesis Simulation Test Bench Development MIMO

What you'll do

  • Architect digital designs for wireless communication projects.
  • Implement fixed-point signal processing blocks in collaboration with systems engineers.
  • Perform RTL coding, simulation, and test bench development.
  • Execute FPGA synthesis and achieve timing closure.
  • Conduct hardware verification and troubleshooting using logic analyzers.
  • Provide technical support to the RF and Software Engineering teams.
  • Develop and maintain FPGA-based designs for advanced wireless systems.

What we're looking for

  • Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields.
  • Minimum 6 years of FPGA design experience (4 years with an MSEE or 2 years with a PhD).
  • Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
  • Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
  • Must be a U.S. Person (U.S. Citizen or Permanent Resident).
  • Preferred experience using MATLAB and communication systems on FPGA or ASIC designs.
  • PhD degree.

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