Browse tech roles

FPGA Vivado Protocompiler HAPS ChipScope Synthesis Place_and_Route Timing_Closure Oscilloscopes Logic_Analyzers Protocol_Analyzers CI/CD Git Python Jenkins PostgreSQL Kubernetes AWS +13 more Show less

Vivado Xilinx FPGA RTL Python Perl MATLAB Fixed_point_design Multiple_clock_domain_FPGA_designs Digital_signal_processing Wireless_communication_systems +6 more Show less

Vivado Lattice Radiant System Verilog Verilog I2C SPI UART USB MIPI DP Python Tcl CI/CD Git CDC FPGA C C++ High-speed serial interfaces +14 more Show less

Vivado Lattice Radiant System Verilog Verilog I2C SPI UART USB MIPI DP Python Tcl CI/CD Git CDC FPGA C C++ High-speed serial interfaces +14 more Show less

FPGA Xilinx Altera Microchip Lattice UVM ASIC DFT Signal_Integrity Python PostgreSQL CI/CD AWS Kubernetes Git Schematics Layout Troubleshooting High_Speed_Board_Design Ethernet Wireless_Protocol PoE_PSE_PD Gigabit_Ethernet Multigigabit_Ethernet 10_Gigabit_Ethernet 25G_Ethernet 100G_Ethernet 400G_Ethernet 800G_Ethernet +24 more Show less

Verilog System Verilog Xilinx AMD Microchip Microsemi SPI I2C UART SpaceWire Gigabit Ethernet PCIe 802.11 Python Tcl Bash Linux C C++ UVM Formal methods +16 more Show less

SystemVerilog RTL/HDL FPGA Xilinx Intel C++ Python Linux ARM AXI PCIe I2C LVDS Ethernet Git JIRA Agile +12 more Show less

Verilog VHDL SystemVerilog Xilinx Petalinux Linux kernel drivers Petalinux Altium DSP concepts image sensors video pipelines high-bandwidth data paths embedded Linux FPGA development Xilinx toolchains HW/SW co-design +10 more Show less

C/C++ Python Perl Ruby Debugging Protocol_Analyzers Oscilloscopes System_Architecture Technical_Debug Validation_Strategy +5 more Show less

Xilinx Vivado FPGA RTL MATLAB Fixed_point_design Digital_signal_processing Multiple_clock_domain_designs +3 more Show less

Verilog SystemVerilog Perl Shell Tcl VCS Verdi GDB ChipScope Xilinx_Vivado Synopsys_Protocompiler Siemens_VPS LPDDR5 LPDDR6 DDR5 DDR6 CXL PCIe USB4 USB3 Synopsys_HAPS Siemens_ProFPGA +17 more Show less