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Analog Design Mixed-Signal Op-Amps Filters ADCs DACs Power Management Battery Management Sensor Interfaces Hardware Prototyping Characterization Debugging Signal Integrity IC Design Cycle +9 more Show less

Siemens/Mentor Graphics Xpedition PWB Layout Schematic Capture High-Speed Digital FPGA HyperLynx Signal Integrity Power Integrity Oscilloscopes Ethernet Network Testers Circuit Card Design +6 more Show less

UVM SystemVerilog Python C++ Java SoC Digital Design Computer Architecture Low Power Architecture Multi-chip SoC Debug High Speed Protocols +6 more Show less

SystemVerilog UVM Python TCL Perl LLM Gate Level Simulation UPF PCIe USB DDR Formal Verification Emulation Simulators Waveform Viewers RTL Verification Methodology +12 more Show less

Analog/Mixed-Signal Circuit Design PHY GDS Verilog HDL Extraction EMIR SigEM SoC Architecture Delay Locked Loops Phase Interpolators Duty Cycle Correctors pre silicon verification +8 more Show less

SerDes Analog Mixed-Signal High-Speed Serial Links NRZ PAM CTLE DFE CDR PLL LDO SystemVerilog Matlab Python VerilogAMS FinFET CMOS PCIe USB MPHY Timing Closure Primetime +16 more Show less

Cameo Magic Draw Capital Enterprise Data Bus Design Microsoft Office Suite Requirements Analysis Integration and Verification Test Execution Vehicle Testing +3 more Show less

Threat Modeling Penetration Testing Python Go Java AWS GCP SQL NoSQL CI/CD SDLC Microservices Distributed Systems AI Cloud Infrastructure +10 more Show less

Python C/C++ Bash Linux Windows CI/CD Jenkins Ansible Perl Tcl LabView I2C Redfish IPMI SPI I3C SVI2 SVI3 PCIe Gen 5 Oscilloscopes +15 more Show less

Photonic Integrated Circuits Silicon Photonics Python MATLAB Ansys Lumerical Luceda IPKISS COMSOL Multiphysics Synopsys OptSim OptoCompiler Cadence Virtuoso Optical Spectrum Analyzers Vector Network Analyzers Oscilloscopes Data Analysis Automated Workflows Semiconductor Fabrication +11 more Show less

Physical Design Synthesis Place and Route Timing Signoff Physical Verification EMIR Formal Equivalence Low Power Verification RTL to GDS Tape-out Foundry Process Nodes +6 more Show less

Verilog System Verilog RTL Design C C++ Python Perl x86 ARM ISA NoC Cache DFT Digital Electronics High-Speed Design +9 more Show less

Innovus Primetime Voltus Synopsys ICC Tcl Python Perl Physical Design EMIR Timing Closure Floorplanning Place and Route DRC +8 more Show less

SystemVerilog UVM Verilog RTL Python Perl C++ Verdi SRAM VLSI Formal Verification LEC ESPCV Perforce Confluence Simulation Toggle Coverage +12 more Show less

Verilog System Verilog UVM Python Perl Palladium Protium Zebu Veloce C-DPI System Verilog Assertions Emulation Mixed Signal Splunk +9 more Show less

System Verilog Verilog UVM RTL SoC Verdi Digital Design Functional Coverage Computer Architecture Logic Design +5 more Show less

Cadence-Innovus Physical Design Place and Route TCL Python floor planning Low Power Design Clock Gating Power Gating Design for Yield Manufacturability +6 more Show less

Allegro Altium PCB Layout Schematic Capture FPGA Microcontrollers SPI I2C UART LVDS Power Integrity Signal Integrity Failure Analysis Root Cause Analysis Oscilloscope Spectrum Analyzer Logic Analyzer DMM Hardware Debug +14 more Show less

Camera Optics Image Signal Processing MATLAB JMP Finite Element Analysis (FEA) Mechanical Modeling Signal Integrity Firmware Rapid Prototyping Failure Analysis Calibration +6 more Show less

SRAM Design RTL Cadence Virtuoso SPICE Model Sim Skill GDS Static Timing Analysis PrimeTime NanoTime WaveView SpiceExplorer Digital P&R DFT Modeling +9 more Show less