Digital Circuit Design Engineer

Apple Inc

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Work type: On-site
Location: Austin, TX
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $203k

$138k most similar roles pay here $263k

This listing doesn't post a salary. Most similar roles pay $165,075–$241,750.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · Digital Circuit Design Engineer

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The Digital Circuit Design Engineer joins the hardware team to ensure all pre-silicon deliveries of custom IPs for Apple SoCs are bug free. The role involves collaborating with circuit and RTL designers to validate functionality, optimize performance, and ensure compliance with architectural specifications. Day-to-day responsibilities include translating requirements into testbenches, running simulation regressions, triaging failures, and performing coverage analysis. You will work on circuits involving SRAMs, register files, and caches while applying VLSI and circuit design knowledge. The role requires proficiency in SystemVerilog, Verilog, UVM, and formal verification tools like LEC or ESPCV. Additionally, you will use Verdi, Cadence Indigo, Perl, Python, and C++ for automation and debugging. Technical tasks include refactoring testbench code for reusability and managing version control via Perforce while ensuring high-quality verification results for complex memory architectures.

Skills

SystemVerilog UVM Verilog RTL Python Perl C++ Verdi SRAM VLSI Formal Verification LEC ESPCV Perforce Confluence Simulation Toggle Coverage

What you'll do

Validate design functionality and ensure pre-silicon deliveries of custom IPs are bug-free.
Translate architectural specifications into SystemVerilog and UVM testbenches including stimulus generation, checkers, and assertions.
Run and debug simulation regressions while triaging failures and performing detailed coverage analysis.
Analyze Toggle Coverage reports to verify complete signal toggling for each design.
Use Verdi and Cadence Indigo tools to debug simulation waveforms and resolve bugs in complex environments.
Develop Perl and Python scripts to automate testbench generation and verification workflows.
Verify custom memory architectures including SRAMs, register files, and caches.
Refactor testbench code to improve reusability and maintainability by removing hardcoded values.

What we're looking for

Bachelor's degree or foreign equivalent in Computer Engineering, Electrical Engineering, or a related field.
Experience using SystemVerilog or Verilog to develop RTL verification testbenches and analyze design behavior.
Experience utilizing Universal Verification Methodology (UVM) or equivalent to develop verification environments including monitors and scoreboards.
Experience performing RTL design verification and debugging using industry-standard waveform and simulation tools.
Experience verifying digital memory and custom circuits such as SRAM, register files, and other IP blocks.
Experience utilizing formal verification tools like Logical Equivalence Checking (LEC) or ESPCV to validate RTL and synthesized netlists.
Experience using Python, Perl, or C++ to automate verification flows, regression execution, and test generation.
Experience with regression management and revision control systems to execute automated suites and track changes.