This role pays less than
75%
of similar roles. Most pay
$152,200–$227,900
— the shaded band above.
At the midpoint, this role pays about
$152k
versus about
$190k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
648 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 615 roles with salary data.
The Physical Design Engineer II joins the Compute Silicon & Manufacturing Engineering team to support silicon design for advanced computer chips like Azure Cobalt. This role involves executing the end-to-end physical design flow from synthesis through place-and-route for smaller designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification. The engineer will manage clock construction, drive methodology exploration to optimize SOC blocks, and influence tools and flows using a data-driven approach. Key responsibilities include RTL to GDS implementation and collaborating with CAD, DFT, and Architecture teams. Candidates should possess expertise in advanced foundry process nodes, low power design methodologies, and PPA trade-offs. The role focuses on solving technical challenges related to high-volume manufacturing and optimizing cloud infrastructure through sophisticated silicon engineering and hardware development.
What does a Physical Design Engineer earn?
Median $177300 from 41 postings across 9 companies.
Execute end-to-end physical design flows from synthesis through place-and-route for smaller designs.
Complete all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Manage clock construction and Clock Tree Synthesis (CTS) for SoC blocks.
Drive methodology exploration to optimize SoC blocks for clock construction and related processes.
Implement the full RTL to GDS transition within the Physical Design domain.
Influence design tools, flows, and methodologies using a data-driven approach.
Partner with CAD and methodology teams to identify and resolve technical flow issues.
What we're looking for
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 1+ year of technical engineering experience.
At least 2 years of technical engineering experience (or equivalent experience).
Experience with production silicon tape-outs in advanced foundry process nodes (preferred).
Experience in low power design methodology for SOC and understanding of PPA trade-offs (preferred).
Familiarity with various clock construction strategies for high speed designs (preferred).
Ability to pass a Microsoft Cloud Background Check.
Must provide proof of citizenship, residency, or other protected status to access export-controlled information.
Colorado Springs, CO+17 days ago
$129,400–$207,000
Physical Design
RTL to Tape-out
Synthesis
Physical Verification
Timing Closure
STA
EM/IR Analysis
Place and Route
Clock Tree Synthesis
Floorplanning
Layout
TCL
Perl
EDA Tools
Colorado Springs, CO+17 days ago
$121,900–$195,000
Physical Design
RTL to Tape-out
Synthesis
Timing Closure
STA
EM/IR Analysis
Place and Route
Clock Tree Synthesis
Floorplanning
Layout
TCL
Perl
EDA Tools
Colorado Springs, CO+138 days ago
$129,400–$207,000
Physical Design
RTL to Tape-out
Synthesis
Timing Closure
STA
EM/IR Analysis
Place and Route
Clock Tree Synthesis
Floorplanning
Layout
TCL
Perl
EDA Tools
IC Design