This role pays less than
61%
of similar roles. Most pay
$169,625–$229,100
— the shaded band above.
At the midpoint, this role pays about
$178k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3553 open roles
on FindRole.
Listed pay typically runs
$165,800–$277,600
across 2740 roles with salary data.
As a Design Verification Engineer, you will join the team to bring up emulation platforms for large Wireless SoCs and Display SoCs along with their mixed signal components. Your daily responsibilities involve developing monitors, checkers, and transactors while creating system level test plans and executing them across cross-functional teams including Architecture, Power, and Silicon Validation. You will build and port models into emulators such as Palladium, Protium, Zebu, and Veloce. The role requires proficiency in Verilog, SystemVerilog, UVM, C-DPI, Python, and Perl to automate test benches and debug failing tests. You will also analyze regressions using Splunk databases, collect coverage to close verification activities, and work with methodology teams to validate new tools. This role focuses on solving complex emulation challenges for large-scale wireless and display integrated circuit designs.
What does a Design Verification Engineer earn in California?
Median $189224 from 46 postings across 7 companies.
System Verilog
UVM
C
C++
Python
Perl
EDA Tools
Digital Design
Computer Architecture
ASIC
High-speed Interface Protocols
Simulation
Regression Analysis
Functional Coverage
Constrained Random Verification