Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $174,149–$225,300 / yr
Posted: 1 day ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k

This role $200k

$141k most similar roles pay here $240k

This role pays more than 54% of similar roles. Most pay $168,500–$229,100 — the shaded band above. At the midpoint, this role pays about $200k versus about $199k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer, you will join the hardware team to design and implement testbench environments and test cases while collaborating with design and micro architecture teams to understand functional and performance objectives. You will examine design specifications, establish robust testbench methodologies, write tests, and generate test coverage for ongoing projects. Your daily work involves developing System Verilog checkers using UVM methodology to verify new debug features, executing regression tests, and analyzing failures by tracing signals with Verdi. The role requires expertise in System Verilog, Verilog RTL, and UVM to ensure design objectives like performance and power are met. You will apply computer architecture knowledge to SoC designs while utilizing functional coverage metrics to verify complex digital circuits and hardware components within the specified project requirements.

What does a Design Verification Engineer earn in California?

Median $189224 from 46 postings across 7 companies.

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Skills

System Verilog Verilog UVM RTL SoC Verdi Digital Design Functional Coverage Computer Architecture Logic Design

What you'll do

Design and implement testbench environments and test cases for hardware projects.
Analyze design specifications to identify functional requirements and areas for improvement.
Develop System Verilog checkers using UVM methodology to verify new debug features.
Generate test coverage and maintain updated test cases for evolving project needs.
Execute regular regression tests to validate design functionality and performance.
Trace signals using tools like Verdi to analyze and resolve test failures.
Verify that designs meet specific power and performance objectives through UVM testbenches.

What we're looking for

Master's degree or foreign equivalent in Electrical and Computer Engineering or a related field.
Experience or education in writing System Verilog/Verilog RTL code to model digital circuits and designs.
Experience or education in using System Verilog/Verilog for developing testbench code based on logic design principles.
Experience or education in using System Verilog/Verilog to debug RTL and testbench code.
Experience or education in developing System Verilog/Verilog to create test benches using randomized tests.
Experience or education in developing UVM testbenches to verify functional correctness.
Experience or education in using UVM testbenches and System Verilog/Verilog to ensure performance and power objectives are met.
Experience or education utilizing Computer Architecture for SoC architecture and design, including functional coverage metrics.

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