SerDes Circuit Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Waltham, MA
Salary
$165,800–$292,400 / yr
Posted
1 day ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $204k
This role $229k
$133k most similar roles pay here $309k

This role pays more than 73% of similar roles. Most pay $166,125–$241,750 — the shaded band above. At the midpoint, this role pays about $229k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · SerDes Circuit Design Engineer

SerDes Circuit Design Engineer will join the high-speed SerDes team to develop advanced analog mixed-signal circuits for wireline transceivers and system-on-chip intellectual property. The role involves evaluating circuit topologies for Rx, CDR, Tx, bias generators, high-speed clock generation, phase interpolators, DLLs, VCOs, and LDOs while optimizing for power, performance, and area. You will collaborate with cross-functional teams to drive block-level specifications, mixed-signal implementations, and behavioral modeling. Key technical requirements include experience with 100+ Gbps NRZ and PAM applications, equalization techniques like CTLE and DFE, and digitally assisted analog design such as LMS based adaptive loops. Required tools and languages include SystemVerilog, Matlab, Python, VerilogAMS, and scripting for automation. The work focuses on high-speed serial links and complex IC development using advanced FinFET technology to solve critical wireline communication challenges.

What you'll do

  • Design and evaluate high-performance AMS circuit topologies for SerDes PHY components like Rx, CDR, Tx, and PLLs.
  • Optimize circuit designs to achieve best-in-class power, performance, and area (PPA) metrics.
  • Lead discussions with cross-functional teams to define block-level specifications and mixed-signal implementations.
  • Develop behavioral models for complex IPs using tools like SystemVerilog, Matlab, or Python.
  • Implement equalization techniques such as CTLE and DFE for 100+ Gbps NRZ and PAM applications.
  • Perform lab testing, debugging, and data analysis to validate circuit performance.
  • Supervise layout and oversee the IC development process from initial definition to high-volume production.
  • Mentor junior engineers in developing circuit components for high-speed IO systems.

What we're looking for

  • Bachelor of Science degree.
  • Minimum of 10 years of relevant industry experience.
  • Deep understanding of analog mixed-signal design with experience in high-speed serial links (preferred).
  • Experience designing various analog mixed-signal circuit blocks such as Bandgap, LDOs, and oscillators (preferred).
  • Understanding of advanced concepts like mismatch mitigation, linearity, stability, and digitally assisted analog design (preferred).
  • Proven track record of working with system/architecture teams for high-speed IO in 100+ Gbps NRZ and PAM applications (preferred).
  • Experience with high-speed digital circuits, Tx/Rx equalization techniques, and CDR architectures (preferred).
  • Proficiency in circuit modeling, lab testing, advanced CMOS technologies, and scripting/automation (preferred).

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