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About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
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As a Design Verification Engineer, you will join the hardware team to ensure bug-free first silicon for specific SoC and IP designs. You will manage all phases of pre-silicon verification, including establishing methodologies, developing test plans based on micro-architecture, and building scalable, portable verification environments. Your daily work involves creating stimulus, checkers, assertions, and trackers while executing design bring-up and regression testing to resolve failures. To achieve high quality and efficiency, you will utilize LLMs and related technologies throughout the development cycle. The role requires expertise in SystemVerilog, UVM, and scripting languages like Python, Perl, or TCL. You will also utilize tools for waveform viewing, coverage collection, and gate-level simulations. Technical focus areas include power-aware verification via UPF and potentially working with serial protocols like PCIe or USB.
What does a Design Verification Engineer earn?
Median $192100 from 79 postings across 10 companies.
Develop detailed test and coverage plans based on the micro-architecture.
Establish scalable and portable verification methodologies for specific IP designs.
Build verification environments including stimulus, checkers, assertions, and trackers.
Execute design bring-up and verify all features under your care.
Debug test failures and resolve bugs identified during regression cycles.
Track and report progress using metrics such as bug counts and coverage.
Utilize LLMs and related technologies to improve verification efficiency and quality.
What we're looking for
Bachelor's degree in a technical subject area.
Minimum 10 years of relevant industry experience or equivalent.
Deep knowledge of OOP, SystemVerilog, and UVM (preferred).
Deep knowledge in developing scalable and portable test-benches (preferred).
Strong experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, and gate level simulations (preferred).
Working experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Excellent knowledge of scripting languages such as Python, Perl, or TCL (preferred).