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Digital Hardware Design Schematic Capture PCB Layout FPGA Embedded Processors PCIe DDR3 DDR4 SDRAM JESD UART SPI 1000BASE-T Mentor Graphic’s Git ClearCase Confluence Logic Analyzers BERTs Signal Intelligence Machine Learning Image Processing +17 more Show less

FPGA VHDL Digital Signal Processing DSP Vivado Quartus Libero MATLAB Simulink Xilinx Altera Microsemi RF Digital Circuit Design Schematic Generation PWB Layout Oscilloscope Logic Analyzer Signal Generator +14 more Show less

FPGA VHDL Digital Signal Processing Vivado Quartus Libero MATLAB Simulink AMD (Xilinx Intel (Altera Microchip (Microsemi Circuit Design Schematic Generation PWB Layout Oscilloscope Logic Analyzer Signal Generator RF Encryption +14 more Show less

HSIO UCIe BOW PCIe AXI CHI CXS.B CXL UA-Link DFT Ethernet PMA Signal Integrity Power Integrity Digital Design Flow Mixed-Signal Design +10 more Show less

ASIC Design RTL Design SystemVerilog Verilog Computer Architecture Synopsys Synthesis Low Power Design Python C++ C Coverage-based Design Verification SoC Interconnects Memory Controllers micro architecture Debugging +10 more Show less

SRAM Design RTL Cadence Virtuoso SPICE Model Sim Digital P&R Static Timing Analysis PrimeTime NanoTime Skill DFT GDS WaveView SpiceExplorer Layout Tools +10 more Show less

RTL SRAM Design Cadence Virtuoso SPICE Static Timing Analysis PrimeTime DFT IR/EM Machine Learning Circuit Design Schematic Capture Power Gating Clock Gating Spice Explorer +9 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design +4 more Show less

Analog Design VLSI Design Hspice Verilog Static Timing Analysis PnR SRAM Compiler Design Schematic Capture Power Efficiency silicon bring up Physical Design +6 more Show less

C C++ Python Verilog SystemVerilog Perl Matlab Vulkan UVM RTL ASIC SoC DSP LTE 5G Wi-Fi Linux Windows Machine Learning +14 more Show less

Verilog HDL RTL Python Perl C UNIX Digital Signal Processing Error Correction Decoding Synthesis STA CDC Checking Lint Checking Gate-level Simulation Silicon Validation Low Power Design IC Development Flow +12 more Show less

ASIC Design Digital Design Mixed Signal Design CMOS Digital Signal Processing Verification Micro-architecture Sensor Integration Analog Design +4 more Show less

CAD VLSI Portable Stimulus Simulation Emulation Digital IC Design Verification Methodologies Design Specifications RF Analog Foundry Process Technology +6 more Show less

ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture +12 more Show less

ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture +11 more Show less

Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture +9 more Show less

UVM Design Verification SoC Integration Design Debug Timing Closure Physical Design test bench setup +2 more Show less

Digital Design Mixed Signal Design FPGA Emulation Silicon Bring-up Characterization Debug MIPI Soundwire I2S SPMI Micro-architecture Verification Emulation Validation +9 more Show less

Mixed-Signal Verification UVM SystemVerilog Verilog VHDL SVA Static Timing Analysis Logic Synthesis Place and Route Formal Verification Python Perl TCL CMOS Bipolar EDA Tools +11 more Show less

Digital Design Mixed Signal Design FPGA Emulation Silicon Bring-up Characterization Debug MIPI Soundwire I2S SPMI Micro-architecture Verification Emulation Validation +9 more Show less