Read Channel Digital Design Engineer

Broadcom

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Quick summary

Work type: On-site
Location: Irvine, CA
Employment: Full-time
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $202k

$134k $253k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $162,000–$241,750.

Based on 240 similar postings.

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About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · Read Channel Digital Design Engineer

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The Read Channel Digital Design Engineer joins the team to focus on hard disk drive read channel digital design, specifically concentrating on digital signal processing and error correction decoding. The successful candidate will work with architects to develop design specifications and perform HDL coding, lint checking, CDC checking, and RTL and gate-level simulation development and debug. Key responsibilities include producing verification and silicon validation plans, reviewing synthesis, STA, and logical equivalence check results, and developing automation for design and verification tasks. Required technical skills include Verilog, UNIX, Perl or Python scripting, and C. Candidates must understand the IC development flow from RTL to silicon and be familiar with low power design techniques. This role addresses technical challenges within the hard disk drive read and write channel domain.

Skills

Verilog HDL RTL Python Perl C UNIX Digital Signal Processing Error Correction Decoding Synthesis STA CDC Checking Lint Checking Gate-level Simulation Silicon Validation Low Power Design IC Development Flow

What you'll do

Develop design specifications in close coordination with architects.
Perform HDL coding, lint checking, and CDC checking.
Develop and debug RTL and gate-level simulations.
Produce comprehensive verification and silicon validation plans.
Review synthesis, STA, and logical equivalence check results with implementation teams.
Provide project resource requirements and schedules to program managers.
Develop automation tools to support design and verification tasks.

What we're looking for

B.S. degree in EE or Computer Engineering with minimum of 12 years of related experience.
M.S. degree or Ph.D. in EE or Computer Engineering with minimum of 10 years of related experience.
Knowledge of Verilog, UNIX, Perl or Python scripting, and C.
Understanding of the IC development flow from RTL to silicon.
Familiarity with low power design techniques.
Ability to work with teams at remote locations and in different time zones.
Hard disk drive and read/write channel knowledge (preferred).
Self-motivation, excellent communication skills, and ability to excel in a team environment.

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