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IC Package Design ASIC RFIC Power Integrity EM Simulation Cadence APD+ SIP HFSS SIWave ADS BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal silicon floor plan +11 more Show less

IC Package Design ASIC RFIC Cadence APD+ SIP SIWave HFSS ADS Power Integrity EM Simulation BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal +10 more Show less

ASIC Hardware Board Design Signal Integrity Power Integrity High-Speed Digital Design Python Cadence Concept Allegro PCIe DDR SerDes Ethernet EMI/EMC Thermal Management Multi-phase Power Conversion Schematic Generation Layout Oscilloscope Logic Analyzer Spectrum Analyzer IEEE Standards 2.5D Fanout Co-packaged Optics Near-packaged Optics +19 more Show less

Finite Element Analysis FEA Structural Analysis Computer-Aided Design Product Development Life Cycle Simulation Model Validation Materials Science +3 more Show less

Cisco Juniper IPSEC MACSEC WAN MAN CAN LAN Type 1 Crypto Solarwinds Switching Protocols Network Design Capacity Planning Performance Analysis Technical Writing CCNA +11 more Show less

Silicon Photonics PIC RFIC Lumerical COMSOL HFSS Spectre ADS SerDes PAM4 NRZ MZM Microring Modulators InGaAs InP CTLE Spectrum Analyzers Vector Signal Analyzers High Speed Oscilloscopes BERT Floor Planning +16 more Show less

Silicon Photonics PIC RFIC Lumerical COMSOL HFSS Spectre ADS SerDes PAM4 NRZ MZM Microring Modulators InGaAs InP CTLE Spectrum Analyzers Vector Signal Analyzers High Speed Oscilloscopes BERT Floor Planning +16 more Show less

human/systems engineering Human Computer Interaction rapid-prototyping Manufacturing Data Analysis Mechanical Engineering Computer Engineering Biomedical Engineering Hardware System Specifications +4 more Show less

Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization +11 more Show less

ASIC Design FPGA Verilog SystemVerilog VHDL RTL Design Python C/C++ Bash SoC Integration DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer +17 more Show less

ASIC Design RTL Design SoC Architecture Microarchitecture Formal Verification AMBA AXI APB Clock Gating Power Gating Timing Optimization high speed networking AI/ML Compute infrastructure, automation Power Estimation +10 more Show less

Hardware Board Design Signal Integrity Power Integrity ASIC High-Speed Digital Design Python Cadence Concept Allegro PCIe DDR SerDes Ethernet EMI/EMC Thermal Management Multi-phase Power Conversion Oscilloscopes Logic Analyzers Spectrum Analyzers Layout +14 more Show less

Verilog System Verilog RTL Design ASIC SoC Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization +11 more Show less

ASIC Design FPGA Design SystemVerilog Verilog VHDL RTL Design Python C/C++ Bash DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer SoC Integration +17 more Show less

RTL Design Verilog System Verilog ASIC SoC Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems +10 more Show less

Verilog System Verilog RTL Design ASIC SoC Synthesis Timing Closure AXI AHB Python HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems Formality Check Silicon Bring-up +12 more Show less

ASIC Design FPGA Design SystemVerilog Verilog VHDL RTL Design Python C/C++ Bash DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer +16 more Show less

RTL Design x86 Computer Architecture Processor Pipeline Memory Hierarchy Instruction Set Architecture Logic Design Python Ruby Perl Silicon Development Lifecycle Tapeout Scripting Automation +9 more Show less

RFIC Design Analog IC Design Mixed-Signal Design Verilog SystemVerilog Python MATLAB Perl Tcl Shell Cadence HFSS RTL Coding Static Timing Analysis DFT SerDes PCIe USB DDR HBM ADC DAC PLL 5G 6G mmWave Signal Processing S-parameters Filter Design Digital Pre-distortion Power Delivery Network SIPI +27 more Show less

C C++ Python Verilog SystemVerilog Perl Matlab Vulkan UVM RTL ASIC SoC DSP LTE 5G Wi-Fi Linux Windows Machine Learning +14 more Show less