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Analog/Mixed-Signal Circuit Design PHY GDS Verilog HDL Extraction EMIR SigEM SoC Architecture Delay Locked Loops Phase Interpolators Duty Cycle Correctors pre silicon verification +8 more Show less

SerDes Analog Mixed-Signal High-Speed Serial Links NRZ PAM CTLE DFE CDR PLL LDO SystemVerilog Matlab Python VerilogAMS FinFET CMOS PCIe USB MPHY Timing Closure Primetime +16 more Show less

SystemVerilog UVM Verilog RTL Python Perl C++ Verdi SRAM VLSI Formal Verification LEC ESPCV Perforce Confluence Simulation Toggle Coverage +12 more Show less

SRAM Design RTL Cadence Virtuoso SPICE Model Sim Skill GDS Static Timing Analysis PrimeTime NanoTime WaveView SpiceExplorer Digital P&R DFT Modeling +9 more Show less

SRAM Design RTL Cadence Virtuoso SPICE Static Timing Analysis PrimeTime DFT Machine Learning Power Gating Clock Gating Digital Circuit Design +6 more Show less

SerDes Analog Mixed-Signal High-Speed Serial Links PLL CDR LDO VCO FinFET SystemVerilog Matlab Python VerilogAMS NRZ PAM CTLE DFE PCIe USB MPHY Scripting +15 more Show less

SerDes Analog Mixed-Signal High-Speed Serial Links FinFET SystemVerilog Matlab Python VerilogAMS CMOS PCIe USB MPHY DFT Scripting Automation Timing Closure +11 more Show less

SerDes High-Speed Serial Links NRZ PAM CDR PLL LDO VCO SystemVerilog Matlab Python VerilogAMS FinFET CMOS CTLE DFE PCIe USB MPHY Scripting Automation +16 more Show less

SRAM Circuit Design RTL SoC GDS DFT IR/EM Machine Learning Scripting Memory Hierarchy Schematic Capture Simulation Silicon Debug Nanometer Device Physics +9 more Show less

Circuit Design Mixed-Signal Post-silicon Characterization Silicon Validation Python Perl Tcl Synthesis Layout Support Data Analysis Automation ATE Testing Bench Instrumentation Voltage Regulation Hardware Security +10 more Show less

IC Design CMOS RF Design Digital Design Cadence Layout Verification Quantum Computing High Performance Computing AI Hybrid Cloud +6 more Show less

SerDes Analog Mixed-Signal High-Speed Serial Links NRZ PAM CTLE DFE CDR PLL LDO SystemVerilog Matlab Python VerilogAMS FinFET CMOS PCIe USB MPHY Primetime +15 more Show less

SerDes Analog Mixed-Signal High-Speed Serial Links PLL CDR LDO VCO FinFET SystemVerilog Matlab Python VerilogAMS CMOS PCIe USB MPHY DFT Timing Closure Primetime +14 more Show less

SerDes Analog Mixed-Signal High-Speed Serial Links NRZ PAM CTLE DFE CDR PLL LDO SystemVerilog Matlab Python VerilogAMS FinFET CMOS PCIe USB MPHY Timing Closure Primetime +16 more Show less

PCB Design Mentor PADS Expedition HDI RF Analog Digital Power Supply BOM Simulation Software Fabrication Assembly NPI Peer Review +9 more Show less

Circuit Design RF Integrated Circuits Superconducting Circuits RF/Microwave Components Vector Network Analyzers Quantum Computing High Performance Computing Hybrid Cloud +3 more Show less

Post-Silicon Validation Circuit Design Analog Digital Mixed-Signal Python C/C++ Power Integrity PVT Analysis Guard-banding Data Pipelines Automated Test Orchestration Oscilloscopes Spectrum Analyzers Transistor Physics PDN Analysis +11 more Show less

SRAM Circuit Design Cadence Virtuoso Python Perl SPICE Static Timing Analysis EM and IR Analysis Formal Verification Layout Schematic Data Analysis Design Automation +8 more Show less

Analog Design VLSI SRAM Hspice Verilog Static Timing Analysis Place and Route Schematic Capture silicon bring up +4 more Show less

Analog/Mixed-Signal SERDES FinFET VerilogA Oscilloscopes Spectrum Analyzers Signal Generators High-Speed Data Converters LDO Regulators +4 more Show less