ASIC Methodology Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Diego, CASanta Clara, CA
Salary
$159,600–$239,400 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k
This role $200k
$140k $250k
below market most similar roles pay here above market

This role pays more than 53% of similar roles. Most pay $162,000–$220,325 — the blue band above. At the midpoint, this role pays about $200k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · ASIC Methodology Engineer

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The ASIC Methodology Engineer joins the DTECH team within the Global SOC organization to enable a state-of-the-art design analytics platform. Working closely with core and SOC teams, the engineer will impact the power, performance, area, and quality of products by developing tools and platforms. Daily responsibilities involve utilizing strong programming skills in Python and hands-on experience with static timing analysis tools such as PrimeTime and Tempus. The role requires a problem-solving mindset and analytical skills to support foundry technology enablement, design automation, and internal and external EDA tools. Candidates may also utilize version control tools like Perforce or Git and possess knowledge of the ASIC RTL-GDSII design flow. This position addresses critical design analysis, optimization, and low power architecture challenges within the ASIC engineering domain.

Skills

Python Static Timing Analysis (STA) PrimeTime Tempus ASIC VLSI RTL-GDSII Git Perforce GenAI LLMs Software Architecture EDA Tools

What you'll do

  • Enable a state-of-the-art design analytics platform for core and SOC teams.
  • Perform static timing analysis using tools such as PrimeTime and Tempus.
  • Develop software and platforms at scale using Python programming.
  • Optimize the power, performance, area, and quality of Qualcomm products.
  • Implement design automation and internal/external EDA tools.
  • Develop and maintain agentic AI systems and GenAI models for real-world solutions.
  • Support foundry technology enablement, analysis, and low power architecture.
  • Manage version control for design projects using Perforce or Git.

What we're looking for

  • M.S. or Ph.D. in Electrical Engineering or Computer Science with 1-2 years of relevant experience with ASIC/VLSI design tools and flows.
  • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
  • Strong programming skills in Python.
  • Hands-on experience with static timing analysis (STA) tools, such as PrimeTime and Tempus.
  • Critical thinking with good software architecture understanding to develop platforms at scale (preferred).
  • Familiarity with GenAI models and experience designing agentic AI systems (preferred).

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