ASIC Design Engineer
Qualcomm
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Market check
How this pay compares to similar roles
This role pays more than 50% of similar roles. Most pay $175,000–$227,300 — the shaded band above. At the midpoint, this role pays about $192k versus about $201k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 623 open roles on FindRole.
Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.
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At a glance
As an ASIC Methodology Engineer within the DTECH team of the Global SOC organization, you will collaborate with core and SOC teams to enable a state-of-the-art design analytics platform. Your daily work involves developing tools and platforms that impact the power, performance, area, and quality of products. You will utilize Python for programming and gain hands-on experience with static timing analysis tools such as PrimeTime and Tempus. The role requires an analytical mindset to solve complex problems within the ASIC RTL-GDSII design flow. Preferred qualifications include knowledge of version control systems like Perforce or Git, software architecture understanding, and familiarity with GenAI models and agentic AI systems. This position focuses on technical challenges involving STA methodology, signoff, foundry technology enablement, and design automation to optimize integrated circuit designs.
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