ASIC Methodology Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CASan Diego, CA
Salary
$153,200–$229,800 / yr
Posted
79 days ago
Freshness
Confirmed live 2 days ago
Closes
Dec 21, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $192k
$141k most similar roles pay here $240k

This role pays more than 50% of similar roles. Most pay $175,000–$227,300 — the shaded band above. At the midpoint, this role pays about $192k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · ASIC Methodology Engineer

As an ASIC Methodology Engineer within the DTECH team of the Global SOC organization, you will collaborate with core and SOC teams to enable a state-of-the-art design analytics platform. Your daily work involves developing tools and platforms that impact the power, performance, area, and quality of products. You will utilize Python for programming and gain hands-on experience with static timing analysis tools such as PrimeTime and Tempus. The role requires an analytical mindset to solve complex problems within the ASIC RTL-GDSII design flow. Preferred qualifications include knowledge of version control systems like Perforce or Git, software architecture understanding, and familiarity with GenAI models and agentic AI systems. This position focuses on technical challenges involving STA methodology, signoff, foundry technology enablement, and design automation to optimize integrated circuit designs.

What you'll do

  • Develop a state-of-the-art design analytics platform for core and SOC teams.
  • Perform static timing analysis using tools such as PrimeTime and Tempus.
  • Develop software platforms at scale using Python and robust software architecture.
  • Implement GenAI models and agentic AI systems into real-world technical solutions.
  • Execute foundry technology enablement, analysis, and design optimization tasks.
  • Manage and maintain internal and external EDA tools and flow integrations.
  • Support the development of low power architecture, methodology, and foundation IP.

What we're looking for

  • A Master's or PhD in Electrical Engineering or Computer Science is required for candidates with 1-2 years of experience.
  • A Bachelor's degree and 4+ years of ASIC design, verification, or integration experience are required for other applicants.
  • A Master's degree and 3+ years of ASIC design, verification, or integration experience are also acceptable.
  • Candidates must have strong programming skills in Python.
  • Hands-on experience with static timing analysis (STA) tools like PrimeTime and Tempus is required.
  • Experience with version control tools such as Perforce or Git is preferred.
  • Familiarity with GenAI models and agentic AI systems is preferred.
  • Knowledge of the ASIC RTL-GDSII design flow and place & route tools is preferred.

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